SU517165A1 - Pulse counter with controllable conversion factor - Google Patents

Description

(54) PULSE COUNTER WITH CONTROLLED RESET ACCOUNT COEFFICIENT

The invention relates to a pulse technique, in particular, to pulse counters on potential logic elements. It can be used in various devices of automation, measuring and

computing technology.

Pulse counting devices are known with a variable conversion factor 11. 2

The first of the known devices for counting I1 pulses with a variable scaling factor contains potential counting T-flip-flops, through-transfer gates and a scaling factor switch, you complete as a set of normally open keys. In the device, the conversion factor is determined by the number of triggers with open keys and can be changed only as a power of two. There are no coefficients other than two (for example, 3, 5, 6, 7, etc.).

This ycTrjcisc3о has a low speed, because. A signal is sent to the i-th trigger through a subsequent GJ

chain of through transfer valves, outside of the large total backplane.

The second of the known devices is more sophisticated, is chosen as a prototype and contains a block; equal to 8 potential logical, ele-laats, consisting of (and -f-1) - stable single-phase trigger and decoder on AND 4-1 elements OR-NOT and And elements, and asynchronous TRS triggers. S inputs of the flip-flops are connected respectively with

4 m outputs (H +1) - stable trigger. T - inputs - with (-1 +1) -f (И -1) m outputs of the same trigger, direct outputs -. respectively, with the inputs of the i-th (i 1, ...,., and) elements of OR-NOT, and inverse video signals with the inputs of all subsequent OR-NOT elements, except the first. The output of the last element OR is NOT connected to the remaining inputs of the Jth elements OR NOT, and the inputs of the elements AND are connected to the control bus to the inverse outputs of the asynchronous S triggers.

However, the known device works kenaezhio.

The aim of the invention is to improve the reliability of the device.

For this purpose, a blocking group is introduced on У1 + 1 elements OR-NOT, two inverters and an output element OR-NOT, and the -th input (and +1) - a stable trigger is connected via the -th element OR-NOT blocking groups to the output of the element OR is NOT a decoder, the clock input is via the first inverter with one of the inputs of the output element OR is NOT the second input of which is connected via the second inverter to the output of the last element OR NOT of the decoder, and the i-th output OR NOT blocking groups. The drawing shows a structural electric circuit of a pulse counter with a controlled conversion factor for the case when q 4. The counter contains asynchronous 0-triggers 1 l-fl 4; a five stable trigger with multiphase control 2, the auxiliary input of which through the inverter 3 is connected to the counting input 4; blocking group 5 on the elements OR NOT 5-1-g5-5; the decoder 6 on the elements OR-NOT b-Mtb-4 and element type 4I-OR-NOT 6-5, the first inputs of element 6-5 connected to the control bus 7, and the output of this element through the inverter 8 is connected to the input of the output element OR - NO 9, the second input of which is connected to the counting input 4. Each output (1 2, 3, 4, 5) of the p-stable trigger 2 is connected to S - to the input of the trigger 1 4 and to the corresponding T - inputs of the trigger 1-1, 1-2, . . , l - (- il), as well as through the element OR-NOT 5 - i - with the corresponding inputs of five-stable trigger 2. Another input of the element OR-NOT 5 - i is connected to the output of the element OR-NOT 6-n The output of the element 4 AND -OR-NOT 6-5 connected to the input of the elements OR-NOT 6-1t6-4 The corresponding inputs of the elements OR-NOT 6-1- :. and 4 AND-OR-NOT are connected to the direct and inverse outputs of Rg- three Gerov 1-1t1-4. Consider the operation of the device, for example, at a given conversion factor of 5. For all remaining coefficients, starting from 1 and ending 16 (ie 2), the device works in a similar way. Setting the conversion factor is the submission of a binary code corresponding to the required coefficient on control panel 7. Coefficient 1 corresponds to OOOO code, 4) code 2O code 10OO, coefficient 3 code 0100, coefficient

Claims (2)

1. Copyright certificate of the USSR № 321956, cl. H 03 to 23/24 of 1971 2. Application No. 2066022 / 26-21 dated October 8, 74, according to which a decision was made to increase the copyright certificate of the same author.