SU515265A1 - Pulse shaper - Google Patents

Description

one

The invention relates to a pulse technique and is intended to form pulses with an increasing or decreasing duration of pulses by a constant value.

Known pulse shaper, containing a multivibrator and a trigger, the output of which through time the driving circuit is connected to a differential amplifier. The strap circuit contains a capacitance that determines the duration of the output pulse 1.

Also known is a pulse shaper containing triggers, the single input of the first of which is connected to the terminal of the shaping signal, and the time is set by the circuit (delay line with taps) 2.

However, such devices are characterized by low pulse shaping accuracy.

The aim of the invention is to increase the accuracy of the generated pulse duration.

This is achieved by the fact that time the looping circuits are made on inverters, and

the output of each trigger through the corresponding inverter is connected to the single input of the subsequent trigger, zero input of the odd triggers directly, and even through the inverter is connected to the terminal of clock pulses.

FIG. 1 given the scheme of the proposed pulse shaper; in fig. 2 shows the voltage plots at the corresponding points of the device, explaining the operation of the pulse former in the case of pulse expansion; in fig. 3 - voltage plots, which illustrate the operation of the pulse shaper in the case of pulse compression.

The pulse shaper contains triggers 1, the outputs of which through inverters 2 are connected to a single input of the next trigger. The zero inputs of the odd triggers are directly, and the even ones through the inverter 3 are connected to terminal 4 of the synchronized pulses of a calibrated duration.

The pulse shaper operates as follows.

Terminal 4 receives the sync pulses (Fig. 2, a) of a calibrated duration and, in the case of pulse expansion, a pulse (Fig. 2, b) of negative polarity on terminal 5 of the generated signal. The occurrence of a signal at terminal 5 will cause a positive potential at the outputs of the flip-flops 1, which will persist until the signal ends at the terminal 5 regardless of the potential at terminal 4. At the end of the input pulse, the potential at the output of the first trigger (Fig. 2c) maintained until zero potential at terminal 4, which sets the first trigger to its initial state. As a result, at the output of the first flip-flop, the central edge of the pulse with respect to the generated signal is delayed by an amount ranging from zero to the duration of the calibrated pulses, depending on the relative position of the falling edges of the pulses at terminals 4 and 5. Thus, the first trigger is tied to the front 4 pulse of the input pulse to the front of the sync pulse. The signal on the other side of the trigger is shown in FIG. 2,

At the output of the second trigger, the back edge of the pulse is removed through the inverter from the output of the first trigger for the duration of the negative sync pulses (Figure 2, d Similarly, the rear of the pulse for the third trigger is generated for the duration of the positive sync pulses, etc. Thus, at the output of the first trigger, the trailing edge of the input pulse is tied to the front of the calibrated pulses, and at the outputs of subsequent triggers

The back of the arm is the same as the duration and pause of the clock pulses. When a positive polarity pulse is applied to terminal 5, a pulse is compressed (Fig. 3).

A change in the pulse duration due to the reference to (| the diameter of the calibrated pulses can be reduced by increasing the repetition frequency of the calibrated pulses. Increasing the delay of the front of the input pulse can be accomplished by increasing the repetition period of the calibrated pulses or increasing the number of serially connected triggers.

Claims (2)

1. US patent number 3742257, M. class. H 03k 17/26, May 1974 2. Avt. St. USSR Ms 429518, M. cl. H 03k 5 / O4, October 1972 ppppppppppppp one one b L ICLCU one e 1 p p g 1 ppppppppp I one in p g 1 p p g one FIG. 2 pppg