SU482340A1 - Device for transmitting information from a vehicle to a checkpoint - Google Patents

Description

(54) DEVICE FOR TRANSFERING INFORMATION FROM VEHICLE TO THE CONTROL POINT

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The invention relates to the field of automatic generation and transmission of information about a moving object at the time of its passage through the control point and can be used for dispatching control and control of transport units, such as locomotives, in open pit mining.

The known device contains a transmitting set installed on the locomotive, and the receiving set located in the control point. The transmitting set comprises a carrier frequency shaping unit with master oscillators, a subcarrier frequency shaping unit for generating a code of transmitted information, a coding switch associated with subcarrier frequency generators, modulators associated with carrier frequency and subcarrier generators, and amplifiers loaded onto emitters and connected inputs with outputs of modulators. The receiving set contains a receiving antenna associated with receiving channels, each of which consists of a series-connected selective amplifier, an amplitude detector, a low-frequency amplifier and a frequency selector; decoders associated with the outputs of the receive channels; output indicators connected to the outputs of the descramblers. The known device provides information transfer from the moving transport unit to the control point, however, the operation of such a device may fail when the vehicle is at the borders of the control point zone at the moment

entry and exit of the latter, when the signal level is close to the sensitivity threshold of the receiver of the receiving set.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by the fact that the receiving set is equipped with an information receiving control unit connected to the receiving antenna, amplifiers, selective and low frequencies, frequency selectors and decipherors of each channel, and for each reception channel of the series-connected detector and integrating element connected through the first matching circuit in series and

one of the memory elements to the corresponding second coincidence circuits, and from the third coincidence circuit connected to the key via

another memory element connected to the first by the corresponding input.

FIG. 1 shows a functional diagram of a transmitting set for the case of transmitting two decimal bits of a code parcel; in fig. 2 - functional diagram of the dividing node; in fig. 3 - functional diagram of the receiving set; in fig. 4 - functional scheme of the descrambler.

The proposed device consists of a transmitting and receiving sets.

The transmitting set is installed on the locomotive and contains a block of formation of carrier frequencies, including the master (stabilized) generator 2 and the dividing units 3-6 connected to it; a subcarrier frequency shaping unit 7 comprising divider nodes 8-I, whose input is associated with a corresponding output of the divider node, for example node 3 of block 1; information encoding switch 12; amplitude modulators 13–16; amplifiers 17-20 connected to respective radiators 21-24. The outputs of the subcarrier frequency shaping unit 7 through the information encoding switch 12 are connected to the corresponding inputs of the amplitude modulators 13-16, the other inputs of which are connected to the outputs of the carrier frequency generating unit 1; the output of each modulator is connected to the input of the corresponding amplifier 17-20.

The dividing node (see Fig. 2) contains a counting circuit made on the flip-flops 25, 26, ..., 27, the input of which is connected to a source of pulse signals; descrambler 28; amplifier 29; differentiating chain 30 and trigger 31. The outputs of the triggers 25, 26, ..., 27 are connected to a decryptor 28, the output of which through the amplifier 29 and the differentiating chain 30 is connected to the zeroing state of the counting circuit, and the counting input of the trigger 31 is connected with the output amplifier 29.

The receiving set (see Fig. 3) is installed at the control point and contains a 32 source kit, made in the form of a slab and laid between the rails, to which the receive channels "1 and" O for each bit of the code parcel formed in series are connected via key 33 selective amplifiers 34-37, amplitude detectors 38-41, amplifiers 42-45 low frequency, frequency selectors 46-49; information reception control unit 50, which includes, in addition to the key 33, memory elements 51, 52 (triggers), coincidence circuits 53-56 (AND gates, detectors 57-60, integrating elements 61-64, circuits 65 , 66 matches (logical “AND” elements). In addition, each receiving channel in the receiving set is equipped with a decimator 67, 68, which are interconnected via the logical element "OR 69.

The element & 66 inputs is associated with the corresponding outputs of the decipherors 67, 68, and

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its output is connected to the input of the flip-flop 51, another input of which is connected to the input of the flip-flop 52 and connected to the decryptors 67, 68, the second input of the flip-flop 52 through the element "AND 65 connected to the outputs of the integrating elements 61-64. The output of the trigger 52 is connected to the control inputs of the And 53-56 elements, and the output of the trigger 51 is connected to the control input of the switch 33. The outputs of the low-frequency amplifiers 42-45 through the detectors 57-60 are connected to the integrating elements 61-64, and through the elements “And 53-56 - to the frequency selectors 46-49.

Descramblers 67, 68 are made the same. FIG. 4 shows a functional diagram of a decipher for one decimal place, for example, a decipher 67.

A trigger memory “1 70, trigger memory“ O 71, which are executed on trigger 72-79, elements “AND 80-88, elements“ OR 89-93, circuit “NOT 94, diode matrix 95, time a pulse delaying and pulse forming element 96. The outputs of the memory triggers "1 and" O are associated with the corresponding inputs of the elements "AND 80-87, the outputs of which are connected to the inputs of the corresponding elements" OR 89-92. The outputs of the elements “OR 89-92 are connected to the inputs of the element“ AND 88, the output of which through the series-connected elements “NOT 94,“ OR 69 is connected to the prohibition bar of the matrix 95 and through the elements 96, 93 to the corresponding inputs of the trigger 72-79. The output of the element “And 88 of each channel along the chain 97 of the coupling with the inputs of the element“ And 66 (see FIG. 3). The inputs 98 of the element "OR 69" are associated with the corresponding outputs of the descramblers of the receive channels "1" and "About other bits of the transmitted number. Outputs 99, 100 (see Fig. 3) are the output switches of decipherors 67, 68. Circuit 101 is the output of the information reading system on which the signal is generated after reading the information. Descramblers are interconnected via a chain 102.

The operation of the device is as follows.

The transmitting set, mounted on a movable object, constantly radiates coded -information in accordance with the position of the encoding switch 12. The transmission of code information is carried out on four carrier frequencies, which are generated by the carrier frequency generation unit 1 (in the given example, a variant using a binary-decimal code is considered, however any other code can be applied). Through modulators 13–16, each carrier frequency is modulated by a subcarrier frequency in accordance with the code generated by switch 12 and fed to amplifiers 17–20, each of which is loaded to a corresponding radiator 21–24.

The carrier frequency generating unit 1 operates as follows. The rectangular pulses from the output of the generator 2 arrive at the dividing nodes 3-6, from the outputs of which signals are taken at a frequency depending on the division factors of the dividing nodes 3-6. Thus, four stable carrier frequencies are formed (the process of forming the carrier frequency by the dividing node is explained in the circuit of Fig. 2). The incoming signal of a certain frequency is divided by the trigger 25, 26, ..., 27 of the counting circuit. The division ratio is set by the decoder 28, at the output of which at the corresponding moments of time a pulse is generated. This pulse is amplified by the amplifier 29 and is fed to the counting input of the trigger 31, and through the differentiating chain 30 to the triggers 25, 26, ..., 27 and returns them to the initial state. The trigger 31 restores the symmetry of the pulse duration and pause and gives the generated carrier frequency.

The subcarrier frequency shaping unit 7 consists of similar dividing nodes 8-I, which operate in a manner described above and form from any carrier frequency (one or more) subcarriers with a given frequency.

With corresponding mutual arrangement of the transmitting and receiving sets, the output signal of the transmitting set through the inductive communication channel enters the receiving antenna 32. The key 33 is normally open and the signal enters the inputs of the corresponding amplifiers 34-37. These signals are amplified by amplifiers 34-37, rectified by detectors 38-41, amplified by amplifiers 42-45 of low frequency and fed to the inputs of the elements And 53-56 and the detectors 57- 60. The elements And 53-56 are closed, therefore there are no signals at their outputs. The signals from the outputs of the detectors 57-60 are fed to the integrating elements 61-64, which restore the signal constant. When the signal carrying the information reaches a given level, the element “And 65” is triggered and the signal from its output switches the trigger 52. The output signal of the trigger 52 acts on the elements “And 53-56 and opens them. As a result, the signals carrying information are sent to frequency selectors 46-49, the output signals of which are deciphered by decoders 67, 68 and, if correctly received, are recorded on triggers 72-75 of memory "1" and triggers 76-79 of memory "O. When information is correctly received, conditions are created to trigger the corresponding four elements "And from the row" AND 80-87 and four elements "OR 89-92. After the elements “OR 89-92” are triggered, the element “AND 88 is triggered, and from its output through circuit 97, the signal goes to the element“ AND 66. The output signal of the element “AND 66 switches the trigger 51, which closes the key 33, stopping the passage of signals zi to the trigger memory “b,“ o.

The operation of the decoder 67 according to the scheme shown in FIG. 4 is as follows. After reading the information, the trigger memory 70, 71 is reset to the initial state by a signal coming in through the circuit 101 from the information collection system at the moment of the end of the information reading. The input signals of the frequency selector 46, which correspond to the number of bit units, are sent to the corresponding trigger trigger 70 of the memory. The output signals of the frequency selector 47, corresponding to the number of zero zeros,

represented by a binary-decimal code, are sent to the trigger memory triggers 71, i.e., the zeros of each bit for any number are transmitted simultaneously with the bit units of that number. With the correct code entry

numbers in memory 70 and 71, i.e., if the direct and inverse codes of the received number correspond, the outputs of the corresponding elements "AND 80-87 generate signals that are received through the elements" OR 89-92 to

the element “And 88. The last one is triggered, but the element“ OR 69 does not receive a signal, since it is inverted by the circuit “NOT 94. Consequently, the signal on the bar 95 of the matrix 95 prohibition also does not come.

Thus, when the information is correctly recorded in the trigger memory 70, 71, at the outputs 99 of the matrix 95, a digit of this bit is generated. If, however, at least in one bit of the binary-decimal code of the number being transmitted, writing to the trigger memory 70, 71 occurs incorrectly, then a bar appears on the prohibition bus 102 that locks all the matrices and generates a reception signal. The same fault signal is used to reset the trigger memory 70, 71 to its initial state. This signal is generated by the elements 96, 93. The reset signal of the memory 70, 71 is generated in the initial state each time a reception failure occurs.

information at least in one bit of the transmitted number. It should be noted that the fault signal in the slit 102 is generated immediately upon the occurrence of a fault in any discharge, and the trigger memory 70, 71 is brought to its original state.

a state, i.e., a device without delay is prepared for the next code parcel reception cycle.

As can be seen from the above description of the operation of the circuit, the reception of code information is provided only when the preset level of the code signal in all channels is reached, which increases the reliability of the device by eliminating the distorted reception of code parcels at the moments of entry and exit of the vehicle from the coverage area. With the limited duration of the communication time between the vehicle and the control point, this circumstance increases the likelihood of reliable reception of information, and, in addition, it becomes possible to use slow-acting data collection systems widely used in open pit mining, since the information is stored without distortions in the receiving set until the end of the process of reading it.

Subject invention

A device for transmitting information from a vehicle to a control point, comprising a transmitter set, in which interconnected carrier and subcarrier frequency drivers are connected via a code switch to transmission channels, each of which consists of a serially connected modulator, amplifier and radiator; a receiving set in which the receiving antenna is connected to receiving channels, each of which consists of a series-connected selective amplifier, an amplitude detector, a low-frequency amplifier and a frequency selector; connected to each receive channel decoders that are interconnected directly and through the element OR, characterized in that, in order to improve reliability in operation, the receiving set is equipped with an information receiving control unit connected to the receiving antenna, amplifiers, selective and low frequency , frequency selectors and decoders for each channel, and consisting for each reception channel from a series-connected detector and integrating element,

connected via a serially connected first coincidence circuit and one of the memory elements to the corresponding second coincidence circuits, and from a third coincidence circuit connected to the key through another

a memory element connected to the first corresponding input,

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