SU470067A1

SU470067A1 - Logical delay element

Info

Publication number: SU470067A1
Application number: SU1930820A
Authority: SU
Inventors: Давид Абрамович Мнухин; Владимир Алексеевич Тихомиров
Original assignee: Калининский З-Д Электроаппаратуры
Priority date: 1973-06-08
Filing date: 1973-06-08
Publication date: 1975-05-05

Description

33

Транзистор 2 удерживаетс в открытом состо нии током разр да конденсатора И через резистор св зи 14.The transistor 2 is held in the open state by the discharge current of the capacitor AND through the coupling resistor 14.

После перехода транзисторов 5, 6, в закрытое состо ние транзистор 2 удерживаетс в открытом состо нии токоМ, переход ш,им через резисторы 7, 8, иереход база-змиттер транзистора 2. Конденсатор 11 разр жен.After the transition of the transistors 5, 6, to the closed state, the transistor 2 is held in the open state by a current, the transition w, through resistors 7, 8, and the transition to the base-emitter of the transistor 2. The capacitor 11 is discharged.

При зар де конденсатора 3 до опорного напр жени делител (резисторы 7, 8) транзисторы 5, 6 открываютс , конденсатор 3 разр жаетс . Врем разр да конденсатора 3 определ ет врем готовности логического элемента задержки к повторному действию.When charging the capacitor 3 to the reference voltage of the divider (resistors 7, 8), the transistors 5, 6 open, the capacitor 3 is discharged. The discharge time of capacitor 3 determines the availability time of a delayed logic element for re-action.

Потенциал в точке соединени резисторов 7, 8 становитс равны-м нулю. Транзистор 2 закрываетс . Папр жение с коллектора транзистора 2 поступает через диод 14 на базу транзистора 5, удержива тем самым аналог двухбазового диода в открытом состо нии. На выходе логического элемента задержки по вл етс сигнал «1. При сн тии сигнала «1 со входа логический элемент возвращаетс в исходное состо ние.The potential at the junction of the resistors 7, 8 becomes zero. The transistor 2 is closed. The coupling from the collector of the transistor 2 enters through the diode 14 to the base of the transistor 5, thereby keeping the analog of the two-base diode in the open state. The output of the delay logic element is the signal "1. When the signal "1" is removed from the input, the logic element returns to the initial state.

Предмет, изобретени Subject Invention

Claims

1. Logical delay element containing the input element “OR-NOT at pp”

transistor connected by a collector through a communication resistor to the base of the ppp transistor of the output element OR-NOT, the time setting RC circuit, threshold cascade, resistive voltage divider connected to the base of the transistor of the output element OR-NO, differing from that, in order to eliminate the appearance of the output signal, at the time of input signal

between the collector of the transistor of the input element OR-NOT and the said connection resistor, a diode is inserted in the direct connection, and between the point of their connection and the common bus the switch is a capacitor.

2. The logical element according to claim 1, characterized in that, in order to accelerate the recovery and increase the stability of the delay time, the threshold cascade is performed on transistors of different types of conductivity connected according to the analogue of a two-base diode connected by a transistor pnp base the element “OR to the collectors of the said elements“ OR-NOT, and the emitter of the pnp transistor - to the output time of the driving RC circuit.