SU445166A1 - Carrier oscillation phasing device for synchronous detector - Google Patents

Description

I

The invention relates to devices for transmitting discrete information over communication channels and can be used in data transmission equipment for phase-locked loop coherent oscillations extracted from a pilot signal.

A device for phasing a carrier oscillation of a synchronous detector in the transmission of a single-band amplitude-phase-modulated signal and a pilot signal, containing a series-connected regenerator connected to the input and a decoder, as well as three delay lines and a phase shifter of the carrier oscillation, phase adjustment in which is carried out by comparison with phase discriminator and time selectors of the moments of selection of the fronts of single signals with the occurrence of gates of the clock frequency of reception nick. With a lag or advance by a single time jump of the gate clock pulse, the phase shifter in the coherent oscillation extraction circuit is appropriately controlled so that the moments of the single clock jumps and clock gate pulses coincide. However, under the effect of interference in the communication channel, the instants of singling out single jumps are shifted relative to their

true position, which leads to a distortion of the output signal of the synchronous detector and to a decrease in the noise immunity of the data transmission equipment.

The aim of the invention is to increase the noise immunity of the device.

This is achieved by the fact that in the proposed device, an amplitude analysis circuit is connected to the input directly and through one of the delay lines, each of the two outputs of which is connected to the corresponding input of the phase shifter through the series-connected delay line and the AND circuit.

The drawing shows a block diagram of the proposed carrier phasing device of a synchronous detector.

The device, when transmitting a single-band amplitude-phase-modulated signal and a pilot signal, contains serially connected regenerator 1 connected to the input of the device and a decoder 2, delay lines 3, 4 and 5, amplitude analysis circuit 6, And 7, 8 circuits and a phase shifter 9 hesitation. (The amplitude analysis circuit is connected to the input of the device directly and through delay line 3. One output of the amplitude analysis circuit is connected through a serially connected delay line 4 and the AND 7 circuit, and the other through a similarly connected delay line 5 and the And 8 circuit are connected to the inputs phase shifter 9. Circuits "And 7 and 8 are also connected to the output of the decoder 2.

The device works as follows.

The signal from the output of the synchronous detector enters the input of the regenerator 1, the delay line 3 and the circuit 6 for analyzing the amplitudes of the precursor and the response precursor for a single impulse. Delay line 3 provides a precursor delay for a single pulse of three clock cycles so that in the amplitude analysis scheme this pulse coincides in time with the post-response pulse. From the output of the delay line 3, the delayed precursor of the response to a single pulse arrives at the input of the amplitude analysis circuit 6, which determines the ratio of the amplitudes of the precursor to the post-injection response to the single pulse. The appearance of a pulse at one of the outputs of the amplitude analysis circuit, for example, at the output connected to the input of the delay line 4, shows that the amplitude of the precursor of the response to a single pulse is greater than the amplitude of the scribe; accordingly, the appearance of a pulse at another output of the amplitude analysis circuit indicates that the amplitude of the precursor of the response to a single pulse is less than the amplitude of the precursor. From the outputs of the delay lines 4 and 5, providing a delay of pulses of 1.5 tact, the signals arrive at the inputs of the circuits And 7 and 8 respectively At the same time, the inputs of the And circuits, in the case of the output of the generator 1 of the combination 0001000, through the decoder 2 of single pulses, tuned to this combination, are supplied with a control signal corresponding to the instant of arrival on one or another circuit of the AND signal, corresponding to the result of comparing the amplitudes of the first the precursor and the first posterior of the response to a single pulse in the combination 0001000 in the amplitude analysis scheme. The signal on the output of hoheme "And 7 appears in the event that the amplitude of the first precursor is greater than the amplitude of the first post-herald response of pa

single pulse in combination 0001000 pa amplitude analysis scheme. The signal at the output of the circuit "And 8 appears in the case that the amplitude of the first precursor. 1 less than the amplitude of the first post-arrestor on the circuit with amplitude amplitudes. The signals from the outputs of the AND circuits are supplied to control the phase shifter 9 in the coherent oscillation extraction circuit.

The subject invention 1i

A carrier phase oscillation device for a synchronous detector in the transmission of a single band amilite-phase-modulated signal and a pilot signal containing a series-connected regenerator connected to the input and a decoder, as well as three delay lines and a phase-shifter carrier wave, different in that, in order to increase the noise immunity, to the input of the device directly and through one

of the delay lines, an amplitude analysis circuit is additionally connected, each of the two outputs of which is connected through a series-connected delay line and an AND circuit, also connected to the output of the decoder, to the corresponding input of the phase shifter.