SU443411A1 - Logical memory - Google Patents

Description

one

A logical storage device is known that contains a drive and a logic array on magnetic cores, stitched by two-sided recording and reproduction coordinate systems and a diagonal bus system, a reversible remote / address addresser, whose outputs are connected to the drive, playback amplifiers, whose inputs are connected to the drive , and exit to the register of regeneration, the outputs of which are connected through the drivers to the corresponding inputs of the drive.

In order to increase the reliability and simplify the device, the playback axes of the logical matrix are connected in series with the drive's drive buses and connected to the inputs of the playback amplifiers, and the recording recording buses are connected directly to the outputs of the regeneration register generators

agonal tires. - to the additional outputs of the drive address decoder. ,

FIG. I shows a block diagram of the proposed device; Fig. 2 is a single bit discharge circuit.

The logical storage device (Fig. 1) contains a drive I and a logic array 2 on magnetic cores, the coordinate buses 3 of which are connected in series with the playback buses 4 of drive I and

connected to the inputs of the reproduction amplifiers 5. The outputs of the latter are connected to the inputs of the register of regeneration 6.

Address Bus 7 Storage I

connected to the outputs 8 of the reverse dechy (|) of the address 9; outputs 10 of which are connected to the diagonal tires II of the logical matrix 2 (the diagonal tires II located below the main diagonal are intended to shift to the left; the diagonal tires II located above the main diagonal are intended to shift right). The main diagonal of the matrix 2 does not have a diagonal tire. Reversible YesDiJ tires are not ishsoh. Shitrator 9 addresses and register 6 reg, d ogling are connected to the control unit via the st 1 12 and 13 COOTTTTirxnTnTPHWH or JJJi-- - SSSbeHHO Discharge accumulator circuit, „„ p ,,, zp ln accumulator chain ha i by limestone. i ciojjjvj, --- - bodies (.: ig.2 is made according to the well-known bridge scheme. „„ The two arms of the bridge, with a common point 14 connected to the same power supply pole, contain discharge buses 4 of the drive I and equalizing resistors 15. The other two arms are connected by a common point 16 to the FORGER of the regeneration register 6. One of these arms contains diode X7, and the other diode and uimv JJ & logical logic 2 records 2. Between the anodes of diodes 17, a coordinate bus 3 is included in the diagonal bridge circuit playback matrix 2, connected to the input of the amplifier 5 playback The proposed device at, transmission time in; 1: the information from accumulator I (Fig. 1) to logical iViaT matrix 2 and the binary word X is shifted back by It-bits to the left or right, provided that ki m, where m - the number of bits in the word X. The information shift is performed in four cycles. In the first cycle, the pulse current -IflC of output 8 on the address bus 7 selected by the decoder 9 is read by cell of accumulator I. If in the read word X the unit contains only in the tth raz de, then eds, directed at the discharge bus 4, the post at the input of the amplifier 5 BOSpro zB.e tim discharge, the output of which is carried out in the recording units i -m discharge rbgistra 6 regeneration. In the next clock cycle, the diagonal bus II located in Fig. 1 below the main diagonal of the matrix 2 is excited to shift the word to the bits to the left by the decoder 9 from output 10, and the drivers of the regeneration register 6 are read. Current pulses in bit tires 18 and 4 of the I-th bit and th. The diagonal bus 1g has a value of +0.5 lo- Current pulses in other bit buses for the considered example are absent, since in all bits the word X, except for t-ro, is all ia.ZIADs1-L. l, rvjjuwio "- i VX J are zeros. As a result, Sov. It., 11 and. j from gz, the fall of the half-currents into one of the hearts of the infrared matrix of liginal matrix 2, located at the intersection of the exciters in ii and 18, is recorded as edinka. All other cores of the matrix 2 are in the zero state. In the third cycle, the cores of the logical matrix 2 are read out, for which, in bus II, which was excited in the second cycle, the forj-i WW J of them, h, h ,. .- -, .. - -, - ,. J The current impulse is measured, the value is equal to -Jo, at the same time ;, kptpppnp pavk -7 /,. After this, the core, which was inserted in the second cycle into a unit, changes the frequency to zero. On tires that penetrate the core, an EFS is induced, with EDS being induced on the bus 3 of the logic matrix 2, fed to the input of the playback amplifier (i + K) -th bit and writes the unit to (G) th regeneration register bit 6, and the emf,: induced on bus 18 included in the L th discharge circuit (Fig.), Is not fed to the input of the corresponding amplifier 5 in play, so as in the chain of action of emf. there are two oppositely connected diodes 17. In the fourth cycle, the shapers of the 6th register of regeneration (LF) are read and the write current is fed into the 7th drive I, as in a conventional MOZU. The current pulses at the outputs of the regeneration register 6 and at the output 8, the decipher of the rator 9 have a velrgchin + 0.5 o. The coincidence of the currents reads the word. which contains a unit in (the bit is written into the cell of accumulator I. The shift to the right is performed in the same way, and only the IF bus, located in FIG. 1, is excited above the main diagonal of the logical matrix 2. When using the 2.5-D the selected playback buses, the coordinate buses 3 of the playback of the logic matrix 2 are connected in series with the tires 4 of the playback of the storage device I, the coordinate buses 18 of the logic matrix 2 are connected to the inputs of the drivers of write write currents before branching along a Reson-rac dshm 1nnam, diagonal II are connected to the additional outputs 10 of the address decoder 9. In the shift mode to the read cycle / 1st and 3rd cycles / in daiifrato- "- / - - - .., -." / - ..-. tgp Tfi-UT-T tgatlg gpt: tzoglt: pn mrmr and gzhre must act half currents (-0.51o} unlike full 1Ol

. -lo} in the reading of a cell of the MOZU of the 2D system.

INVENTION PRAJT

A logical memory containing a drive and a logic array on magnetic card 1; ah, stitched to two write bus and memory

A bus and a diagonal bus system, a reverse address decoder, the outputs of which are connected to the drive, amplifiers of output, the inputs of which are connected to the accumulator, and the outputs - to the regeneration register, the outputs of which:: are connected through the form-. rotors to the corresponding inputs of the accumulator, characterized in that, in order to simplify ycTpoiicTsa and increase its reliability, the coordinate reproduction buses of the logical matrix are connected in series with the accumulator's output buses and connected to the inputs of the playback amplifiers, and regeners of the register of regeneration, diagonal tires - to the additional outputs of the address decoder of the drive.

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