SU439917A1 - Phase Shift Code Converter - Google Patents

Description

(54) CODE-SHIFT PHASE TRANSMITTER

The controlled circuit 3 of the delay of pulses is intended for the delay of the pulses of the master oscillator within the period of their succession and a value proportional to the additional code of the least significant bits of the initial code of the phase of the transducer. A schematic solution of a controlled delay circuit has several options, for example, based on a shift register or on-line circuits with voltage comparison, iroirational to the code of the lower bits of the output phase code with a linearly decreasing voltage.

In the proposed device, the circuit 3 of the delay is made in the form of Liia 4 delays with taps, decoder 5, valves 6 and two schemes "OR 7 and 8.

The two-commaid switch 9 pulses and switches the pulses generated by the wired delay circuit and the inputs of the variable phase circuit.

The switch also has several design options.

In the proposed converter, it is made according to a two-channel scheme in the form of series-connected delay lines 10 and 11, inverters 12 and 13, gates 14- / 7, and OR 18 and 19 circuits.

The AND 20 circuitry decodes the detected state of the reference phase counter, its output signal is controlling for the pulse switch.

The variable phase circuit includes a phase intersection counter 21, generating initial signals, forming an output variable phase voltage, and a group of high-order gates 22, by means of which the initial phase counter 21 is set.

Shapers 23 and 24 of the output voltages of the reference and variable phases convert the original rectangular signals taken from the counters of the reference and variable phases into voltages of the desired shape, for example, sinusoidal.

In addition, the addendum converter contains, respectively, 25 and 26 lower and upper order tires of the source (input) phase code, output buses 27 and 28, which support the second variable phase.

The device operates as follows.

The impulses of the master oscillator are fed to the input of the counter 2 phase support, from the high-priority trigger of which (as well as necessary and from the lower-order bits) the initial signals are taken, and the output voltage from the reference voltage of the required form .

At the same time, the pulses / o from the master oscillator 1 pulses are fed to the output of the delay line 4, in which oi, displaced from the tap to the tap by one eighth of their follow-up period, form eight series of nonius pulses / 1-fs dividing the period

outgoing pulses / o into eight equal parts.

The signals from the bus 25 lower bits of the current value of the input phase code are fed to the inputs of the decoder 5, and one of the outputs of which, depending on the value of the phase code, establishes the enabling potential.

Maurimer, if the phase code is equal to 000.010.101 (Fig. 2), then the resolving potential is installed on the bus 101 of the decoder 5. This potential opens the corresponding string 6, and the series / g pulses are passed to the input of the OR 7 circuit.

The pulses from the output of the OR 7 circuit are fed to the input of a two-command switch 9, which passes them to the counting input of the counter 21 of the variable (or reference) phase, for which signals from the output of the counter 2 are fed to the control input of the two-command switch 9 and to the control inputs of the group valves 22 high-order bits that perform the installation of the counter 21 of the variable phase by assigning to it the current value of the high-order bits of the phase code (in this example, code 000.010).

The phase variable counter 2 forms the input sigals that are converted by the phase former shaper 24 to the output terminal of the variable phase bus 28.

To ensure high reliability of the converter, a dual command switch .9 is a dual channel switch.

Sigals from all bits of counter 2 are supported by the phase inputs to the inputs of the & 20 circuit, the output of which generates a signal at a certain counter state (in this example, with the code 111.110; in general, the i-bit counter of the irp state corresponding to).

This sigal arrives at the input of the first of two successively connected delay lines 10 and 11 (the lines delay the input sigals by three quarters and a half of the follow-up period of the specifying emulsions / o, respectively), which form two gainers for two channels of the input emulsions of the switch.

In the device under consideration, all the states of the counter 2 of the reference phase, with the exception of the state 111.110, the signals at the output of the AND 20 circuit, and, consequently, the output lines 10 to 11 of the delay, are absent, and the inverter outputs 12 and 13 are, whereby the valves 14 and 75 are open, and the valves 16 and 17 are closed. Therefore, the input pulses of the two-command switch 9 of the first channel, taken from the OR 7 circuit, pass the gate 14 and the OR 18 circuit and connect to the counting input of the counter-21 of the perepemnaya phase (at this time, the input pulses of the second channel, taken from the OR 8 control circuit 3 delayed circuit, no).

When the counter 2 of the reference phase reaches the state 111.110, the output of the "And 20, and

After a certain time and on the outputs of the delay lines 10 and 11, the signals of the control gates appear. At the time of these signals, the valves .16 and 17 are opened, and the valves 14 and 15 are closed. At the same time, the next input imiuls of the first channel is not fed to the input of the variable phase counter 21, since the valve 14 is closed, but through the valve 16 and the OR 19 circuit to the control inputs of the group of higher bits of the valves 22, which change the state of the counter 21 through its installation inputs.

The state 111.110 of the counter 2 is held for only one period of the following oscillation of the master oscillator /, therefore all subsequent input pulses of the first channel of the two-commutation switch 9 are directed to the counting input of the counter 21 of the variable phase.

The second channel of the two-command switch 9 is completely analogous to the first.

High reliability of operation of the converter is ensured by the fact that the variable phase counter is set to the initial state coincides with one of the clock clock emuli along which the counting pulses are formed, therefore, after the initial state of the counter is set to damp the transient mode, the same time remains in its elements as after changing its state but counting imiuls; In addition, the counting emulsion is blocked for the time of setting the initial state of the counter, which eliminates a failure in the individual bits of the counter due to the simultaneous action of the counting and setting signals on them.

The phase offset between the same states of the reference and variable phase counters (Fig. 2) is 2 / g of the time period for the imitation of the master oscillator. This value in the binary number system is written in the form 000.010.101, which exactly coincides with the input code of the phase, if the numbers that separate its bits are separated from the leading decimal places.

With different values of the input phase code, the phase shift between the states of the reference and phase phase counters is proportional to the phase code, and its high bits correspond to an integer number of periods of the master oscillator contained in the phase shift, and the smaller ones to the number of periods.

Thus, in the proposed converter, setting the magnitude of the phase shift between the output signals of the reference and variable phases is performed with an accuracy of up to 5 fractions of the follow-up emulsion time of the master oscillator, while in the known device the discrete value of this setup is a whole period.

From the comparison of the proposed converter with the known one, it can be seen that the accuracy of the proposed device is eight times higher than the known one, and the accuracy of the proposed converter can be not increased by proportional complication of its controlled imulse delay circuit.

PREDIMET and 3 obrete and and

The code-phase shift converter containing a master pulse generator connected to a phase opacity counter, a phase phase counter, connected to a discharge, with 5 coarse gates of higher bits of the code being converted, controlled imulse delay circuit, implemented as a delay line with taps, through valves, controlled by the decoder of the lower 0 bits of the code being converted, are connected to the inputs of two OR circuits, characterized in that, in order to improve the accuracy and transformation pulse generator, introduced the scheme "And and

5 two-command “pulse switching unit, made in the form of two series-connected delay lines, the input of which is through the circuit“ And connected to the outputs of the reference phase counter, and the outputs are connected to the permitting inputs of the first and second valves directly and through the inverters with the third and fourth permitting inputs valves, the other inputs of which are connected respectively to the output of the first “OR and

5 to the input of the first valve and to the output of the second “OR” circuit and the input of the second fan; the outputs of the first and second valves through the third scheme "OR connected to the pulse inputs of the group of high voltage bits, and the outputs

the third and fourth valves through the fourth circuit “OR, are connected to the counting input of the variable phase counter.

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f (od ipastjt Fig 1