SU436452A1 - SELECTOR ASYNCHRONIC SIGNALS - Google Patents

Description

one

The invention relates to multi-channel communication systems and can be used s data transmission devices.

A selector of asynchronous signals is known, which contains a polling switch, each of its n outputs is connected to the first input of the corresponding one of the transmission paths, each of which in turn contains an information input node connected by the first output through the first input of the polling node and the first output of the transmission path to the corresponding one of the n inputs of the information output node, and on the output of the input information node at each transmission cycle through the first input and output of the programming node and the second output of each transmission path are connected to co Bet1Stvuyuschemu of claim polling switch inputs, said first input of each of the n transmission paths connected within the transmission path to the second input polling node and the second input of each transmission path connected to the first input of the input unit informaschii.

However, in the well-known selector, asynchronous signals of communication lines and uniform selection of selective signals at the output of the information output node lead to uneven delays. The delay between the input of the signal to the selector from the communication line and the output of this signal from the output of the selector varies widely. The inconsistency of the delay of signals during their selection makes it impossible to determine the exact temporal position of the signal during information processing.

In order to detect delays of signals passing through the selector, in each of the transmission paths between the output of the programming node and the second input of the input node

The information is switched on by its first input and output coincidence circuit, the second input of which is connected to the output of a block of time common to all para transmission channels. FIG. 1 shows the block diagram of the proposed selector; in fig. 2 - time diagram of his work.

The selector of asynchronous signals contains node 1 input information, node 2 programs, switch 3 demand, node 4 survey, block 5

time, coincidence circuit 6, and information output node 7.

Block 5 time selector consists of a generator of 8 pulses, the counter 9 pulses, node 10 of the survey and the adder 11.

The information output unit 7 includes a block of random assemblies, to the inputs of which the outputs of the interrogation nodes 4 are connected, and its outputs are connected to the inputs of the buffer storage device (BDU). Buffer memory. Interrogates

in cycles of its internal generator of the information output node 7 serves to align the flow of information and to allocate the time required for processing the information.

The arrival of the next signal at the input Bx 1 in the node 1 of the input of information fixes the number of the next channel, and the message transmitted to this channel. The code of the channel number is compared with the codes that are stored in node 2 of the program, which, when the codes match, extracts the equality signal of the codes received at the inputs of the interrogation switch 3 and the matching circuit 6. The last time code opens and passes the input of the information input node 1. Switch 3 olrosa will generate a polling signal.

: According to a polling signal, a time code, a channel number code and a message code transmitted via this channel, fixed in the information input node 1, are transmitted to the information output node 7 via the polling node 4 and fixed there.

Then, according to the read cycles, the information from the node 7 is evenly distributed through equal intervals of time to the output of the selector.

FIG. 2 shows input signals Bx1, Bx2 and Bhp of three asynchronous four-channel communication lines with time division channels, reference pulses a and markers b of these lines, four (1k, 2k, 3k) channels were selected for each line. The pulses a and b are fed to the inputs of Bx1, Bx2 and Bhp selector, respectively.

The selector of asynchronous signals selects all channels arriving at its inputs, but only the necessary ones, i.e., channels indicated by thickened horizontal lines for the first input of the selector Bx1-first dripped 1k, for the second input Bx2 the third channel Hc, for Vhp - the third and fourth channels Zk and 4k. The said channels are input through the memory of the program node (for example, by a punched card) through the input 12. The reference pulses Xi, Xz, xs and Xi in time coincide with the equality signals of the codes that select the nodes of the 2 programs. The polling signals I-III generated by the polling switch 3 are used to transfer information from node 1 to node 7.

The polling switch 3 is made according to an adaptive scheme and selects polling signals only on demand from the 2 program nodes, therefore, in the diagrams, each of the assigned channels has its own specific polling signal.

The first interrogation signal enters into the BZU of the information output unit 7 codes relating to the first channel of the first path, the second interrogation signal enters into the BZU codes related to the third channel of the second path, etc.

The proposed selector contains clock pulses T produced by the internal generator of the information output node 7, and the allocated output channels Output 1 are counting pulses in generator 8.

Ta: 1 tovy§ pulses, z / i, 2/2, 3 and t / 4 in time coincide with the beginning of the output of the information of the corresponding channels to the output of Oy1 selector.

An analysis of timing charts shows that the delay of signals passing through the selector of asynchronous signals can be determined by the formula

y - x - y ,,

where is the current time of issue

output 1 output selector;

X - current signal arrival time

code equality from node 2 programs.

The selection of the fourth channel of the third path occurs with a delay of knots - Xs 2T (T is the period of the pulse following the polling pulse survey), and to select the third channel of the same path occurs without delay, since r / 4 is Xi Q.

The delay time of the signals is allocated as follows.

In the b block of time, the generator 8 pulses produces counting pulses. Counter 9 pulses recalculates them to form codes

consecutive number of numbers (time). At the moment, the code pulse appears from the equality of the codes from block 2 of the programs, the code of the number from the counter 9 pulses through the coincidence circuit 6 is bitwise, is transferred in parallel to

node 1, and then via polling node 4 is stored in the RAM. When information is output from the BZU by clock cycles T, the input of the polling node 10 receives signals for polling the counter 9 pulses. The contents of the counter as

decreasing (y) is sent to adder I.

At the same time, in the adder, as a subtracted (x), the code of the number, previously fixed in

moment of occurrence of the signal of equality of codes. The difference allocated to the OUT2 of time block 5 is the magnitude of the delay of the e-dial. Uncertain signal delay is possible in other subsequent transmission units,

processing and display included at the OUT1 of the selector, which is performed using the additional input 13 of the selector, in this case, the total delay of the signals can be determined by taking into account the delay in the indicated blocks.

In the proposed device, the selection of signals of equality of codes by nodes of 2 programs occurs asynchronously. Time bound

these signals are carried out from one generator of 8 pulses with an accuracy of the period of its oscillations t. To achieve the necessary accurate delay metering (the appropriate frequency and stability of oscillations should be chosen.

Subject invention

An asynchronous signal selector containing a polling switch, each of its output pins is connected to the first input of the corresponding transmission p path, each of which, in turn, contains an information input node (Connected by the first output via the first input of the interrogation node and the first output of the transmission path to the corresponding of the n inputs of the information output node, and the second output of the information input node in each transmission path through the first input and output of the programming node and the second output of each transmission path is connected to

corresponding to the n inputs of the polling switch, and: the 11th input of the driver from the transmission paths is connected inside the transmission path to the second input of the polling node, and

The second input of each transmission path is connected to the first input of the information input node, characterized in that, in order to detect delays of signals passing through the selector, from the transmission paths between the output of the programming node and the second input of the information input node, it is turned on with its first input and the output of the coincidence circuit, to the second input of which is connected the output of the block of time

for all n transmission paths.

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