SU436346A1 - DEVICE FOR TRANSFORMING THE SEQUENCE OF PULSE COMPENSATION OF THREE-LEVEL SIGNALS - Google Patents

Description

one

The invention relates to the field of computing and can be used to convert a sequence of impulses into a sequence of three-level signals suitable for transmission over a limited bandwidth path.

A device is known for generating three-level signals whose spectrum does not contain components adjacent to zero frequency.

However, the temporal and low temperature stability of the parameters of the known device leads to a decrease in the conversion accuracy and a decrease in the reliability of operation.

In order to increase the accuracy of conversion and increase the reliability of the -work in the proposed device, a sequence of pulses is converted into a sequence of three-level signals formed from segments of a quasi-sinusoidal signal.

For this, the outputs of the second and third AND circuits OR are connected to another input of the control unit, the other output of which is connected to the information input of the reversible binary counter, and one of the trigger outputs is connected to another input of the first AND circuit, and its output and the zero output of the descrambler is connected to the outputs of the blocking node, the input of which is connected to the input bus of the device, and its third output through the node of the zero level setting is connected to the adder. The third inputs of the second and third circuits are connected to the corresponding outputs of the decoder.

The drawing shows the block diagram of the proposed device.

The device contains a master oscillator 1, a binary divider 2 of the number of pulses, an electronic key 3, a trigger 4, the first circuit "And 5, a reversible binary counter 6, the second and third circuits" And 7 and 8, the control node 9, the decipher 10, the differentiating circuit 11 , block 12 weights, adder 13,

the scheme "OR 14, the blocking node 15 and the node setting zero level 16.

In the initial state, the master oscillator 1 generates a sequence of rectangular pulses, of which in the binary divider 2

the number of pulses are generated by the sync pulses arriving at the source of information. At the same time, the pulses from the output of the master oscillator 1 are fed to the information input of the electronic key 3, which, with a certain polarity of the signal at the control input, passes a pulse sequence to its output.

The trigger 4 is in a single state and prepares a signal from its output.

the first scheme "And 5 and includes reverse

binary counter 6 is in direct counting mode, preparing the counter to count the pulses arriving at its information input.

The other inputs of the second and third circuits And 7 and S from the output of the control node 9 are fed to the resolving potential, and to the third inputs to the inhibiting potential from the corresponding outputs of the decoder 1i.

When the input bus of the device receives a positive polarity signal synchronous with the pulse generated by the binary divider 2 of the number of pulses, the electronic key 3 passes its output of a sequence of rectangular pulses to the PA. Of these pulses, the differentiating circuit 11 separates two series of short pulses, one of which goes to the first input of the control unit 9, and the second to the first inputs of the second and third circuits And 7 and 8.

As the circuits "And 7 and 8 are closed with third inputs, then the signals at the outputs of these circuits are absent, and the trigger 4 remains in one state.

The first series of short pulses from another output of the control unit 9 is fed to the information input of the reversible binary counter 6, and the input of the installation of the specified counter from the output of the binary divider 2 number of pulses through an open circuit "And 5 comes sync pulse under which initial state. To increase the reliability of the installation of a reversible binary counter 6 and the compensation of a single pulse acting at the time of installation on the information input, the installation pulse must be longer than the pulse duration at the information input of the reverse binary counter 6.

After the installation process is completed, the reversible binary counter 6 under the action of pulses at the information input is successively transferred to state 1, 2, ..., p. The cells of the reverse binary counter are turned on to the decoder 10, so that in the counting process on O, 1, 2, ..., in the outputs of the decoder, rectangular pulses having the same amplitude appear successively. These pulses pass through a block of 12 weights, the transmission coefficients for each of the outputs of which are selected in a certain way.

The pulses from the outputs of the block of 12 weight coefficients are added to the adder 13, as a result an upward portion of the positive half-period of the quasi-sinusoidal signal is formed at its output.

When the reverse binary counter reaches a state corresponding to code n, the third input of the "And 8" circuit 8 from the corresponding output of the decoder 10 enters the resolving potential. The AND 8 scheme opens and transmits a single pulse to its output, under the action of which the trigger 4 switches to a bullet state, and signals from its outputs connected to the control buses of the reversible binary counter 6 transfers the latter to the countdown mode.

At the same time, the signal from the output of the circuit "AND 8 through the circuit" OR 14 is fed to another input of the control unit 9, which, after switching the counting direction, excludes one pulse from the pulse series at the information input of the reversible binary counter 6. This is necessary to ensure upward and downward symmetry downstream sections of the quasi-sinusoidal signal, which ensures high accuracy of the conversion.

To prevent the device from self-blocking, the control node 9, after excluding one pulse at the information input

the reverse binary counter 6 outputs to the other inputs of the second and third circuits "And 7 and 8 inhibit potential.

Then, under the action of the pulse sequence at the information input, the reversible binary counter 6, included in the countdown mode, is successively transferred to the state (p-1), (p-2), ..., 1, 0. At the output of the adder 13, a descent is formed the positive half-period of the quasi-sinusoidal signal.

By the end of the positive polarity pulse on the input bus, the output of the adder 13 will have completed the formation of a positive half wave, the upstream portion of which is formed in the forward counting direction, and the downward portion — in the reverse counting direction in a reversible binary counter 6. This increases the output symmetry the signal, since the output signal steps having the same amplitude are formed using the same cells of the descrambler, the block of weighting coefficients, and the adder. . When a signal arrives at the input bus

the negative polarity of the electronic key 3 is closed, and the pulse input sequence is not received at the information input of the reversible binary counter 6. At this time, the blocking node 15 is opened, which by its potential blocks the reversible binary counter 6 from its output. This improves the stability of the circuit by eliminating accidental failures of the reversible binary counter b due to interference in the power supply circuits, impulse noise, etc. , the input to the input bus of the device signal of negative polarity.

At the same time, the blocking node 15 by a signal from one of the outputs turns off the zero output of the decoder 10, and a pulse from the third output turns on the node for setting the zero level 16, which supplies the potential 13 to the potential corresponding to the average level of the sum signal. In such a state, the circuit is located before the next pulse of positive polarity arrives at the input bus.

When the next pulse of positive polarity arrives at the input bus, the electronic key 3 opens again, and the information input of the reversible binary counter b, included in the countdown mode, receives pulse signals, under the action of which the reversible binary counter from the zero state switches sequentially to the state t, (t-1), ..., (and + 1) (t is the capacity of the reversible binary counter).

At the corresponding outputs of the decimator 10, square-wave pulses appear, which, after passing through the block of 12 weight coefficients, are added to the adder 13, forming a portion of the negative half-wave of the quasi-sinusoidal signal.

When the reverse binary counter B reaches the state (+1), the resolving potential will come to the third input of the circuit "And 7" from the corresponding output of the decipher 10.

The "And 7" scheme transmits a single pulse to its output, under the action of which the trigger 4 switches to the unit state and switches the reversible binary counter 6 into the direct counting mode. At the same time, the signal from the circuit “AND 7” through the circuit “OR 14 is fed to another input of the control unit 9, which excludes one pulse from the series of pulses at the information input of the reversible binary counter 6, and then gives to the other inputs of the circuits“ And 7 and 8 the inhibitory potential for exclude self-locking device.

After switching the counting direction to the information input of the reversible binary counter 6, included in the direct counting mode, a sequence of pulses continues to arrive, which transfers the counter from the state (n + 1) to the state (/ g + 2), (n + 3) , ..., (t-1), t. In adder 13, the formation of a negative half-wave of a quasi-sinusoidal signal ends. The steps of the negative half-wave having the same amplitude, as well as the steps of the positive half-wave, are formed using the same descriptor cells, a block of weighting coefficients and an adder, which ensures high accuracy of conversion.

If the next information message on the input busbar is positive, then the device operation cycle repeats, i.e., the sync pulse from the binary divider 2 output of the number of pulses through the first AND 5 circuit sets the reversing binary counter 6, which compensates for the information pulse the input, and then the reversible binary counter, included in the direct counting mode, sequentially switches to the state 1, 2,. . ., n, etc.

Thus, with a positive signal polarity on the device’s input spindle, the information input of the reversing binary

counter 6 receives a pulse sequence that switches it from one state to another. In each counting cycle, a sync pulse arrives at the input of the reversible binary counter, which allows restoring the device to normal operation in the event of a reversal binary counter 6 or trigger 4. Periodic reversing binary counter 6 when a positive field pulse arrives on the input busbar the meter is completely blocked when a negative polarity impulse arrives at the input busbar; it ensures high stability of the device with respect to fading and interference.

Before being fed into the line, the constant component is eliminated from the signal formed in the adder.

With an increase in the frequency of the master oscillator 1 and a corresponding increase in the capacitance m of the reversible binary counter 6, the output waveform more and more approaches a sinusoidal one.

Subject invention

A device for converting a sequence of pulses into a sequence

three-level signals containing the master oscillator, the output of which is connected to the input of the binary divider of the number of pulses connected to the output through the first circuit “And to the input of the reversing binary installation

the counter, whose outputs through the decoder are connected to the inputs of the weighting unit connected by the outputs to the inputs of the adder, the output of the master oscillator is connected to the information input of the electronic

a key whose control input is connected to the input bus and the output through a differentiating circuit to one of the inputs of the control unit and the second and third AND schemes, the other inputs of the second and third And schemes are connected to one of the outputs of the control node, and the outputs with the trigger inputs, the outputs of which are connected to the control women. reversible counter, zero-level installation node, blocking node and OR circuit, which are different in that, in order to increase the accuracy of conversion and increase the reliability of the device, therein the outputs of the second and third circuits AND via OR circuit are connected to another input of the control unit , the other output of which is connected to the information input of the reversible binary counter, and one of the trigger outputs is connected to another input of the first AND circuit, and its output and the zero output of the decoder are connected to the outputs of the blocking node whose input with schinoy input device, and its third output through a zero level setting unit is coupled to the adder, the third inputs of the second and third circuit "and associated with respective outputs of the decoder.

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