SU433511A1 - - Google Patents

Description

one

The invention relates to the field of computer technology and can be used to create digital integrating machines.

A digital integrator is known that performs an integration operation with automatic variable scaling and contains a register of the integrand function, the output of which is connected to the first input of the adder, the second input of which is connected to the first input of the digital integrator, the multiplication unit, the first input of which is connected to the second input of the digital integrator, the output of the multiplier through the increment block is connected to the first output of the digital integrator, the second and third outputs, the third and fourth inputs of which are connected En respectively with the first outputs and the first inputs of the block of signs and the correction block, the second input of the block of correction is connected to the second output of the block of signs.

However, the functionality of this integrator is limited in the sense that it does not allow for analyzing the contents of the / register and, therefore, adjusting the size of this register and the scale of the integrand function.

The aim of the invention is to enhance the functionality of a digital integrator.

This is achieved by introducing additional blocks: an analysis block, following the information in the r / -register and determining the possibility of changing the length of the discharge grid and the scale of the integrand, and the shift block, which performs rescaling (/ -register according to orders coming from correction block.

It is known that the following scale relationships correspond to each digital integrator.

  Uri +.

qii

(one)

P V + P

de LPU is the number of bits used in the register of the integrand,

Shu is the scale factor of the integrand of the function y,

mq-u. - scale increment factor at the input Dx,

gpri is the scale increment factor for input Dg /, gpi is the scale factor for output increment DT. In the known digital differential analyzers, these scales are calculated when preparing the task for the solution and do not change later. Such a choice of scales cannot provide high speed and accuracy of the solution over a sufficiently large integration interval. The state of the function at this integration step can be judged by the following features: 1. opportunities to scale up the function 1, if, 5 O, if, 5, where g / your is the machine value of the integrand; 2. the possibility of increasing the length of the discharge grid of the machine 1, if 1p „/ r„ ash, About, if Lp ,, n „ash. where “mash is the real length of the discharge grid of the machine; d. j 1, if;, О, if Lp l „„ „, where“ min is the number of bits allocated for the extension of the integral; 4. Overflow of the discharge grid 1, if o, if V & ai 1 All these signs are generated in the analysis block and transmitted to the feature block, where they are the initial values for determining the possibility of increasing the scale factors and 5, (2) B ,, , where Bn, Bqu, Bree are indications of the possibility of increasing the scale factors that are supplied to the feature blocks of other decision blocks according to the switching scheme; EM, Equ, Ei -r - signs of the possibility of increasing the same scale factors coming from other decision blocks. In addition, information about the possibility of increasing the scale coefficients Ey, Equ, Eri, as well as signs W, BL, OIL, f are received in the correction unit, where they are used to solve the correction equations for the system of scale relations (1): a,. /, .4 V b (x TV / W4) V VKVU - (.- xVfifj (LvvgVMAv V «.VU (.l.Bi by a, a (E, l, d, Jd, / l), XX dj-. , V («« bn,) d,) V d ,. / J (3) ft,:, а „/, V b (d: c С VV d.) VV". AL bJ (,) J () bL () lb, am (/E,,jd.,).d. ((;; v) №vg 6, (/, vv g-FAV -. (X {(d, JB, / l, (E ..a.,). where they, yu, uz are negative, abx, by, bz are positive increments of the scale factors; fnqu, headings, and, respectively, generated in this correction block and transmitted e to correction blocks of other decision blocks connected to the data according to the task set scheme; dx, dy, dz are negative, a / f, ly, Iz are positive increments of the same scale factors obtained by this correction block from others; flm. (bm ) —negative (positive) increment of the scale factor τ supplied from the correction block to the shift block, as an order to halve (halve) the machine value of the function; UL, (L) -negative (positive) increment of the number of bits allocated for the representation of the integrand function, supplied from the correction block to the shift block as an order to reduce (increase) by one bit the used length of the discharge grid (/ -register of the digital integrator Obviously, the correction unit, solving the system of equation (3), allows to reconcile the change in the scale of the function and the used length of the discharge grid of the digital integrator with the scales of the input and output increments. integrator. It consists of register 1 of the integrand function, the output of which is connected to input 2 of adder 3, with inputs of gates 4 and 5, delay line 6, input of valve 7 and inverter 8 of circuit 9 for detecting overflow of analysis unit 10. Delay line 6 outputs and the inverter 8 is connected to the inputs of the valve 11. In addition, the output of the delay line 6 through the inverter 12 is connected to the input of the valve 7, the second input of which is connected to the output of the register 1, and the output is connected to the input of the valve 13, to the second input of which the output of the valve is connected and the output is connected to the inputs

valves 14 and 15. The outputs of the valves 4, 5, 14, 15 communication buses 16 are connected to the inputs of the block 17 signs and block 18 correction. The feature block 17 is connected by communication buses 19 to the outputs of the characteristic blocks of other decisive blocks connected to the data, buses 20 to the inputs of the characteristics blocks of the same blocks, and communication buses 21 to the input of the correction block 18, which is connected to the communication buses 22 with the outputs of the correction blocks of other solvable blocks, one of the outputs is with communication buses 23 with the inputs of the same blocks, and the other with communication buses 24 is connected to the inputs of the assembly circuit and the valves 25-30 of the shift block 31. The output of the trigger marker 32 is supplied to the second inputs of the valves 25, 27, 29, and the second inputs of the valves 26, 28, 30 are connected to the inverse output of the same trigger. The outputs of the valves 25-30 are connected to the inputs of the circuits of the Assembly 33, 34, 35, the outputs of which are connected respectively to the inputs of the valves 36, 37 and 38, the second inputs of which are connected to the output of the adder 3, and the output of the valve 36 is connected via a delay line 39 to the input of the circuit 40 build. The output of the valve 37 is connected to the second input of this circuit, and the output via the delay line 41 is connected to the input of the valve 42. The output of the assembly circuit 43 is connected to the second input of the valve 42, and the output is connected to the input of the assembly circuit 44, the second input of which is connected to the output of the valve 38 and the output is connected to the input of register 1, the input of trigger marker 32, and the input of multiplication unit 45. The second input 46 of this block is supplied with an independent variable, and the output is connected to the input of the block 47 increments. The output of this block is connected to the input 48 of the adder 3 or to the input 46 of the multiplication unit 45 other solvers, their blocks connected to this according to the switching circuit. The inputs 49-52 of the valves 14, 15, 4, 5 are the inputs of the signals Uan, meaning Bf, cx, respectively. The input 53 of the assembly circuit 43 is the input of the signal t / zp. The trigger marker 32 is set to zero on the bus 54.

The digital integrator processes the information provided in the modified additional code. The information advances the lower bits ahead.

The digital integrator works as follows.

At each step of the decision, the analysis unit 10 using a valve 4 and a pulse at the input 51) corresponding to the lower significant register register 1 determines the possibility of increasing the length of the discharge grid of the register 1 by means of the valve 5 and the pulse at the input 52 ((/ s ,), corresponding to the selected minimum length of the discharge grid, it determines the possibility of reducing the length of the discharge grid, using the circuit 9 generates an overflow signal

  and „.ip-1 / and„ -ip-1.

where Un-Vn-i (Un,) is the major and minor sign bits of the code (inverse sign bits) and signals of the possibility of increasing the scale of the integrand function

in „Un-Un-i V Un-1 Un-1,

which, according to the impulse corresponding to the highest sign bit 49 (Uan) and the youngest sign bit 50 (t / sn-i) supplied

the inputs of the valves 14 and 15 along the tires 16 are entered into the feature block 17. In the feature block 17, on the basis of the information about the possibility of increasing the scale coefficients coming from the tire 19, as well as

Based on the information on the behavior of the function at this integration step, coming from analysis block 10 via tires 16, the system of equations (2) is solved and you generate (one signs of the possibility of increasing

scaling factors that are transmitted via the tires 20 to the inputs of the attribute blocks of other decision blocks. In addition, signs of the possibility of increasing the scaling factors are also received via bus 21 to correction unit 18. On the basis of these signs, and the signals coming from the analysis unit 10 via tires 16, and the increments of the scale factors coming from the correction blocks of other crucial blocks via bus 22, the system of equations (3) is solved and orders are generated for changing the scale of the function and bit length grids, as well as increments of scale factors that are distributed to the rims 23

into correction blocks of other decision blocks. Based on the rescaling indications generated in the correction block, the new value of the integrand function obtained on the adder is corrected.

3: g / g + 1 g / i + Ar / i + i. In this case, in the shift block 31, first opens one of the gates 25, 27, 29 and, therefore, through the assembly circuits 33. 34, 35 - one of the gates 36, 37, 38 and the number of bits allocated for the function representation changes, and then upon arrival of the marker unit to the input of the trigger 32, one of the gates 26, 28, 30 and, respectively, one of the gates 36, 37, 38 is turned on and the contents of the register 1 are shifted (to the left or

right, i.e., multiplication by or). The shift is carried out using delay lines 36 and 37. A valve 42 and an assembly circuit 43 serve to multiply the sign bit when the contents of register 1 are shifted to the left. The rest of the digital integrator is no different from the known one. At each step of the solution, a new value of the integrand r /, - + i i / i + -fAi / j + i is formed on the adder 3. while iji comes from register 1,

and Ar /; + 1 from the output of another integrator. This new value yi + is corrected in the shift block 31 and then entered into register 1, and is also fed to the input of multiplier 45, where it is multiplied by the increment of the positive variable at input 46, i.e. A2, j.i g /,. The resulting unquantized increment value of the integrand function is quantized in the increment block 47 and transmitted to the inputs 46 or 48 of other digital integrators.

Subject invention

A digital integrator containing a register of the integrand function, the output of which is connected to the first input of the adder, the second input of which is connected to the first input of the digital integrator, a multiplication unit, the first input of which is connected to the second input of the digital integrator, the output of the multiplication unit is connected to the first output of the digital multiplier integrator, second and third outputs, third and fourth

the inputs of which are connected respectively to the first outputs and the first inputs of the attribute block and the correction block, the second input of the correction block is connected to the second output of the attribute block, characterized in that, in order to extend the functionality, a shift block and an analysis block are entered into it, the input of which is connected with the register output of the integrand function, the output of the analysis unit is connected to the second input of the feature block and to the third input of the correction unit, the second output of which is connected to the first input of the shift unit, the second input to Secondly, it is connected to the output of the adder, the output of the shift unit is connected to the input of the register of the integrand function and the second input of the multiplication unit.

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