SU392562A1 - TIME EXTRACT DEVICE - Google Patents

Description

one

The invention relates to a pulse technique and can be used in equipment for various purposes.

A time delay device is known which contains an input key stage made according to the Darlington scheme on two pnp transistors, the collectors of which are connected via resistors to the negative pole of the power source, the output threshold stage on the pnp transistor connected according to with a common emitter, to the base of which an RC circuit is connected, the common connection point of a resistor and a capacitor of which is connected via a semiconductor diode connected in a direct field for charging current, the time of the driving capacitor, to the collector Darlington transistor circuit output. However, such a device has a large recovery time and does not delay the disappearance of the signal.

The purpose of the invention is to delay the disappearance of the signal and reduce the recovery time of the time delay device.

For this, in the proposed device, a capacitor is connected between the collector and the emitter of the input transistor of the Darlington circuit.

FIG. 1 shows the principal electrical circuitry of the device proposed; in fig. 2-input and output voltages.

The input stage is made according to the Darlington scheme on transistors J p 2, the collectors of which are connected to the negative pole of the power source through resistors 3 and 4. The output threshold stage is performed on the transistor 5 according to the scheme with the common, the emitter. An RC circuit consisting of a resistor p and a capacitor 7 is connected to the base of transistor 5. The connection point of resistor 6 and capacitor 7 is connected to the collector of transistor 2 via diode 8. Between the collector and the transistor emitter / capacitor 9 is turned on. 12. The device input is terminal 13, and the output is terminal 14.

In the initial state, transistors I and 2 are closed, transistor 5 is open, capacitors 7 and 9 are charged. When pokleug-sh1 C1; drive U, transistors 1 and 2 open at input terminals 75, capacitor 9 is discharged through transistor 1, discharge of capacitor 7 starts through resistor 6 and the base of transistor 5. Resistor 6 is selected in such a way that discharge time the capacitor 7 through it is equal to t {FIG. 2). After the end of the charge of the capacitor 7, the transistor 5 closes, a signal appears at the output terminals 14. After the termination of the signal3

The Lc transistor / closes and the transistor 2 remains open due to the charging current of the capacitor 9. The resistor 3 is selected so that the charging time of the capacitor P through it is t.

After charging the capacitor 9, the circuit returns to its original state.

The invention

A time delay device containing an input key stage made according to the Darlington scheme on two p-ga / 7-transistors, the collectors of which are connected to the negative pole through resistors

power supply, disconnection; (threshold cascade on a pnp transistor connected in a common emitter circuit to the base of which is connected to an RC circuit, the common connection point of the resistor and capacitor of which is connected through a semiconductor diode included in the direct polarity for charging current, the time of the driving capacitor, to the collector of the output transistor of the Darlington circuit, characterized in that, in order to delay the disappearance of the signal and reduce the recovery time, between the collector and the emitter of the input transistor of the Darlingt circuit connected to the capacitor.

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