SU386441A1 - DEVICE MANAGEMENT OF MEMORIZING BLOCK - Google Patents

Description

one

The device can be used in automation and computing.

A memory block management device is known, comprising two rows of cores with clock windings, write windings, preparation distribution windings and read distribution windings connected to two read drivers and two write drivers, and diodes connected by anodes to the output ends of the windings placed on them. read and zaisi Such a device is difficult and not reliable in operation.

Into the proposed device, two preparation current formers are entered: And two additional rows of cores. The beginnings of the clock windings of the cores of the first and second additional rows are connected to the current preparation driver, and the ends to the beginnings of the clock windings of the cores of the first and second main rows, respectively. The beginnings of the windings of the recording of the cores of the first and second additional rows are connected to the ends and distribution windings of the core preparation of the second and first main circuits, respectively, and the ends to the diodes of the diodes whose cathodes are combined and connected to the negative potential. The beginnings of the distribution windings are combined for the cores of the first and second additional rows and connected respectively to the writing current driver, and the ends of the distribution windings of the cores of the additional rows are connected to the anodes of the diodes. This simplifies the device and improves its operational reliability.

The drawing shows the basic electrical scheme of the device.

The device contains 1n 2 preparatory current generators, readout current formers 3 and 4, write current formers 5 and 6, clock windings 7, write windings 8 connected through decoupling diodes 9 to the negative busbar power supply Etp, distribution windings W preparation, distributive windings // readings connected via diodes 9 to storage unit 12, distributive windings 13 and cores 14-25, ..., n, of which 14, 18, ..., n-3 are the cores of the second additional p yes, 15, 19, ..., p-2 - cores of the first main p, yes, 16, 20, ..., p-1- erdechniki second core row, 17, 21, ..., n - cores of the first additional row. The clock windings and windings of the recording pass through all the cores; on the cores of the main rows, additionally allocate the distribution windings of preparation and reading, and on the cores of the secondary rows - the distribution windings 13.

To simplify the description of the operation of the circuit, the current driver of the initial installation of the cores and the general winding of the installation of the initial state of the cores, which penetrates equally all the cores, except one, for example 16, are not shown in the drawing.

The operation of the device is based on the impedance principle of current distribution, which consists in the fact that the core winding has a large resistance to the current flowing through it, if the core is re-magnetized by this current. If the reversal does not occur, the resistance of the winding is minimal.

Before starting work on the common winding of the initial installation of the cores, a current pulse is passed, which sets the core 16 to the state of "one, and the other cores to the state of" zero. It is assumed that the current entering the beginning of the winding, marked with a dot in the drawing, sets the core to "ssl.

Then the shaper is fired. The impulse of the current preparation of the former / passes through the clock windings of 7 cores 17, 21, ..., p of the first additional row and cores 15, 19, ..., p-2 of the first main row yes, on the winding 5 of the core 15 recording, remagnetization its state "unit", the distribution winding 10 of the core 16, the winding 8 of the core II, its reversal into the state of "unit", the diode 9 to the power source. The passage of current through this strut is determined by the small resistance of the multi-turn winding 10 of the core 16, which does not peremagnetize during the passage of the preparation current pulse. On the windings of 10 cores 20, 24, ..., p-1 due to the large resistance, small currents of interference flow, which remagnetize the cores 20, 24, ..., p-1 from the state "zero to state" unit by size 0.5-0.6 Vg. The cores 19, 23, ..., p-2, 21, 25, ..., p do not change their state under the influence of interference currents.

After the cores 15 and 17 are switched from the “zero to the state”, the unit starts the shaper 3 and the read current pulse passes through the distribution winding of the core 16, diode 9, the selected addressing circuit of the storage unit 12. On the windings 11 of the cores 20, 24 , ..., p-1 insignificant interference currents flow, which remagnetize the cores to a state close to "unity". When the switch operates correctly, the cores 20, 24, ..., p-1 under the influence of noise currents in the distribution of the preparation current and the read current are re-magnetized by up to 1.8-1.9 Bg. The readout current distribution pulse in the selected circuit of block 12 has a minimum leading edge duration, since the inductive resistance of the winding 11 of the core 16 is minimal due to the fact that the core 16 is magnetized by the preparation current deep along the flat part of the hysteresis loop.

At the end of the preparation current and the read current, the shaper 5 is triggered and the write current pulse passes through the distribution winding 13 of the core 17, diode 9, through the selected writing winding of the block 12. Minute interference currents flow through the windings 13 of the cores 21, 25, ... since the cores 21, 25, ..., p, being previously in the state of the recording current in the state of "zero,", re-magnetized to the state of "one". In this case, the cores 21, 25, ..., n can remagicize by an amount up to

1.8-1.9 Вг.

The passage of the preparation current prepares a sample of the next direction, since the core 15 is in the state of "one, and the cores 19, 23, ..., n-2 in the state of" zero. Next, a sample is taken of the second address of block 12. A start-up pulse is fed to the input of shaper 2, the preparation current pulse of which passes through the clock windings 7 of cores 14, 18,. . ., P-

- 3 second additional rows and cores 16, 20, ..., p-1 of the second main row, remagnelling the cores 16, 20 to the initial state "zero, winding 8 of the recording core n-1, reversing it to the state" unit, winding 10 of core 15, winding 8 of core 14, reversing it to the state of "unit, diode 9 to the power source. The preparation current passes through this circuit because the winding 10 of the core 15 does not have a resistance to the passing current, while the cores 19, 23, ..., n-2 re-magnetize from the state "zero to state" unit currents .

After non-magnetization of the cores 14 and p-1, the state of the former 4 is started into the state of a unit distributed preparation, and the readout current passes through the winding of the core 15, diode 9 selected

block address 12. On the windings 11 cores 19, 23 ,. .., p-2 insignificant interference currents flow, which remakes these cores into a state close to "one". At the end of the preparation and reading current, the shaper 6 is started and the write current pulse passes through the winding 13 of the core 14, diode 9, to the selected block address 12. Through the windings 13 of the cores 18, 22 ,. .., p-3 minor currents flow

interference that the cores do not magnetize from the state "zero to state" one. The recording current distribution along the described circuit occurs because the core 14, previously magnetized by the preparation current, is in the state

"Unit, does not overmultiple write current."

Then, the module publishes the third address of the block 12. Shaper 1 triggers, the current pulse of which passes

on the windings of 7 cores first