SU383045A1 - MULTIPLAYER OF TWO FREQUENCY SIGNALS - Google Patents

Description

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Multipliers of two frequency signals are known, including counters, triggers, and coincidence circuits.

The purpose of the invention is to obtain a continuous output frequency signal, to increase the accuracy, speed and simplify the multiplier.

The scheme of the proposed device shown in the drawing.

The proposed multiplier contains the key /, which pulses the reference frequency / e in accordance with the control signal; block 2 of the formation of time intervals proportional to the period supplied to it by one of the multiplied frequencies (for example, /); counts; to 3 reference frequency; counter 4 of the second frequency multiplied; The unit 5 compares the states of the counters 3 and 4 connected by its inputs to the outputs of the bits of the counters and the output to the inputs of the reset of the counters to the similar states and the input of the driver 2.

The proposed multiplier works as follows.

At the input 8 of the multiplier, a fixed frequency / e is supplied from the reference frequency generator, which is fed to the input of the counter 5 of the reference frequency via the key A which is opened in accordance with the control signal coming from the output of the reference frequency.

tel 2 of the time interval by the time proportional to the period of one of the multiplied frequencies (in this case fi). The duration of the time interval formed is CT, where the 7th signal period is often / I

you fa, K is the selected number of periods T, which determines the accuracy of the device and the speed of the device.

When a key / signal arrives at the control input from block 2, the frequency fa passes to the input of counter 3 and fills it during the CT time. Here, the number recorded in counter 3 is CT.

Another signal of the frequency multiplier / 2 is constantly fed to the input of the counter 4.

The outputs of the bits of the counters 3 to 4 are connected to the inputs of the comparison unit 5, which, if the counter codes are equal, produces a pulse that triggers the time interval 2. This pulse also controls the reset of the counters to i-like states and goes to the output of the multiplier.

Thus, after each installation of the initial state of the counter 3, the number 3 is formed in it. Since the pulses at the output of the device occur when the codes in the counters are equal, the frequency of these pulses is equal to

LL / HL

L - L

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l.,

that is, the output frequency is proportional to the product of the input frequencies.

The main factors determining the accuracy of the multiplier operation are the counter size, the frequency value / e, the choice of the coefficient K. These values can be obtained high accuracy and speed with a simple multiplier circuit.

Subject invention

A multiplier of two frequency signal levels containing two counters with combined reset inputs, the input of one of which is connected to the source of one of the frequency signals, a key, a block for p, p MIR01VA1N1II time

intervals and a comparison unit, the output of which is the output of a multiplier, characterized in that, in order to obtain an output continuous frequency signal, increase accuracy, speed and simplify the device, the input of another counter is connected to the output of a key, one of the inputs of which is connected to the output of the forming unit time intervals, one input of which is connected to the source of another multiplied frequency signal, another input of which is connected to the output of the comparison unit and the reset inputs of the counters to the initial state, and Comparison block moves are connected to the outputs of the bits of the counters.

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Output