SU381176A1 - - Google Patents

Description

DEVICE FOR SYNCHRONIZATION BY CYCLES

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The invention relates to apparatus for transmitting information using pulse code signals.

Arrangements are known for cycle synchronization of a marker signal transmitted in a group pulse-code signal at evenly distributed positions of each cycle, containing successively connected shift registers and a synchronization state indicator, one of the inputs of which has a marker marker failure signal.

The purpose of the invention is to accelerate the entry into synchronism. It is achieved by the fact that, in the proposed device, the outputs of the shift registers are connected to the cyclic shift identifier inputs, the flow of which, in turn, is connected to the marker input of the fault signal detector and to the control inputs of the recording pulses directly and through the status indicator no synchronicity. An additional output of the latter is connected to the inputs of the initial setup of the shift registers, and the output of the last shift register is connected to the input of the first through a recording pulse switching unit and directly to the second input of the marker signal failure detector, the third input of which is connected to the corresponding input of the recording pulse switching unit and is input devices.

The drawing shows a functional diagram of the device.

The device contains a write pulses switching unit (i), shift registers 2i-2, cyclic shift identifier 3, a marker 4 signal failure detector and a synchronism state indicator 5.

The delay time of each shift register is equal to the duration of the sub-cycle, and the total delay time of all successively included shift registers is a cycle. The outputs of the shift registers are connected to the inputs of the identifier 3. The output of the last shift register 2n is connected to the fault detector 4 p to the second input of the switching unit /. The two control inputs of the switch unit are connected respectively to the outputs of the identifier 3 and the indicator 5, the second indicator output being connected to the inputs of the initial setting of the shift registers. The device input and the output of the opiover 3 are connected to the inputs of the fault detector 4, the output of which is connected to one of the inputs of the indicator 5, and the second input of the indicator is connected to the output of the identifier.

In the established synchronization mode for cycles, the input signal through the switching unit / does not pass, and signals from the output of the last register arrive at the input of the first shift register. Thus, in the identifier 3, for each nodcycle, one pulse is output to the fault detector 4, which at the moments of arrival of pulses from the identifier compares the characters at the input of the device with the characters from the output of the last register. If the comparison fails, i.e., the characters in the input do not match the characters from the output of the last shift register, a pulse is given to the indicator 5, which puts the device into the synchronism state search mode. In this case, the switching unit / switches on the input of the first shift register a signal from the input of the device. In addition, when going into the synchronization state search mode, a zero is recorded in all cells of all registers except the first cell of the first register, and a unit is recorded in the first cell of the first register. During the cycle time, the unit enters the output of the last register and switches the operation mode of the switching unit /. In this case, the impulses from the output of the last register begin to arrive at the input of the nerve register. However, at those moments when the marker signal or its cyclic shift is detected in the opoder 3, the signal from the input of the device enters the input of the first shift register. As a result, in those positions where there is no regular alternation of marker symbols in all subsequent cycles, the marker signal is not detected. If several cycles of the alternate marker signal or its cyclic shift are detected only once per subcycle, the indicator switches the device to the steady state. If, for the subcycle, no cyclic shift of the marker group is detected, the initial search mode is activated, in which the input signal is fed through the switch / input to the first register. Thus, the described device provides the entry into synchronization over cycles during a time almost equal to the minimum possible detection time of a regular marker signal in a random sequence of binary symbols of the received pulse code signal. The subject of the invention is a cycle synchronization device containing successively connected shift registers and a synchrometer status indicator, to one of whose inputs a marker siali fault detector output is connected, characterized in that, in order to accelerate synchronization, the outputs of the shift registers are connected to the identification inputs cyclic shifts, the output of which, in turn, is connected to the control input of the marker signal failure detector and to the control inputs of the recording pulses switching unit both directly and through the synchronization state indicator, in addition, the auxiliary output of the latter is connected to the inputs of the initial setup of the shift registers, and the output of the last shift register is connected to the input of the first through a switching pulse recording unit and directly to the second input of the marker error detector, the third input of which connected to the corresponding input of the write pulse switching unit and is the device input.