SU374731A1 - DEVICE FOR SYNCHRONIZATION OF PULSE ASYNCHRONOUS CODE - Google Patents

Description

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The invention relates to a pulse technique and can be used in control circuits of discrete automatics devices, radio code control systems and in pulse digital information transmission systems.

A device for synchronizing pulses of an asynchronous code is known, which contains an input block, a command code and clock feed busses, comparison stages, command triggers, AND, OR, NOT, delay elements and a synchronization trigger. However, using a known device, it is impossible to solve the problem of synchronizing the output pulse with many incoming asynchronous signals simultaneously.

The purpose of the invention is to increase the number of simultaneously synchronized signals varying with a frequency lower than the clock frequency.

For this, the inputs of the comparison cascade are connected to the code buses and to the outputs of the command triggers, and its output is connected via the circuit "NOT to one input of the cascade" AND, the other input of which is connected to the clock supply bus through two consecutively connected delay elements, and the output of the cascade " And connected to the input of the cascade "OR, the output of which is connected to the input of the installation to" zero synchronization trigger, and another input through the delay element is connected to the output of the cascade "And, one input of which is connected to the single output of the trigger of synchronization ation, and the other input through three delay elements is connected to the clock feed bus; “The unit outputs of the command triggers are connected to the inputs of the OR cascade, the output of which is connected to the cascade input“ AND, another input of which is connected to the clock pulse supply bus through the delay element, and the output to the installation input of the “synchronization trigger unit”; “The zero input of each command trigger is connected to the output of the corresponding cascade“ I, one input of which is connected to the clock supply bus and the other via the cascade “NOT to the corresponding command code feed bus, and“ the single input of each command trigger is connected to the output of the corresponding cascade "And, one input of which is connected to the bus clock, and the other - with the corresponding bus command code.

The drawing shows a functional block diagram of the proposed device.

The device contains an input unit /; cascade 2 comparison; triggers 5 teams; cascades 4-6 cascades 7, 8 cascade 9 trigger 10 synchronization; items

11-14 delays; tires 15 - 16 - respectively, the filing of the command code and clock pulses. Bus 15 A control potential code is sent to block 1, and clock pulses are sent over bus 16 to the same node. From the input circuits of the block ./ "O and" 1 control, its potential code on buses 17 is fed to cascade 2 for comparison with "O and" 1 code recorded on the trigger of 5 commands received on buses 18.

Upon arrival of the clock pulse, the triggers 3 are set to the states corresponding to the control potential code, the change frequency of which is less than the clock pulse frequency. Since the control potential code is not synchronized with the clock pulses, the latter can be partially cut off in the input device, which could lead to a false operation of the controlled device.

The proposed device does not allow the trigger pulse to be sent to the control unit if the triggers of 3 commands after the clock pulse were set were set to a state that did not correspond to the control potential code. If the code was recorded correctly, then the output potential of the cascades 2 and 7 is set, and the output potential of cascade 9 is set to the inhibitory potential, so that the cascade 5 is closed. Cascade 6 is opened by the resolving potential from the output of cascade 7. The clock pulse, having passed through element 14, enters through cascade 6 to the input of trigger 10 of synchronization and sets it to “1. The trigger 10 unit arm opens the cascade 4. From the output of the element 14, a pulse through two other consecutively connected elements 11 and 12 interrogates the cascade 4 opened by the synchronization trigger 10. From the output of cascade 4, a trigger pulse is issued. The same impulse through element 13 and through cascade 8 sets synchronization trigger 10.

If the control potential code continues to be present on the command trigger control circuit, then with the arrival of the next clock pulse, the process of issuing the trigger pulse is repeated. If the control potential code either arrives or changes at the moment of arrival of the clock pulse, and for this reason the "pulse cutoff" occurs, then the code recorded on the command triggers will not be identical to the control potential code. In this case, the output potential of the comparison stage 2 will be the inhibitory potential, and the output resolution of the stage 5 will be resolving. At the output of cascade 9, the potential is the opposite of the potential at the output of cascade 2 of the comparison, i.e. in this case, it is resolving, and cascade 5 will open. A clock pulse passes through element 14, through cascade 6, open allowing

potential from the output of the stage 7, and sets in "1 trigger 10 synchronization. From the output of the element 14 delay pulse through element 11, cascade 5, open resolving potential from cascade 9, and through cascade 8 enters the trigger 10 synchronization and sets it in "O. Pass through the element 12 of the delay pulse arrives at the cascade 8, but does not pass through it, since

0 trigger trigger 10 is already in the zero state, and in cascade 4, the inhibitory potential. As a result, the output of the cascade 4 will not trigger a pulse. Since, by hypothesis, the frequency of the change of the control potential code is less than the frequency of the clock pulses, the next clock pulse will not come at the moment of change of the control potential code, and the code will be rewritten on the command triggers without fail. As a result, the output potential of the comparison stage 2 will be the resolving potential, and the output potential of the stage 9 will be the inhibitory potential. As a result, in the process of issuing a triggering pulse, the synchronization trigger 10 will not be set to the zero state, and the triggering pulse will be issued from the stage 4, and then through delay element 13 and the stage 8 the synchronization trigger 10 will be set to the zero state. In this way, a triggering pulse is provided only if the code is recorded on the command triggers without a fault.

Subject invention

A device for synchronizing pulses of an asynchronous code, containing an input block, command code and clock pulses, comparison cascades, command triggers, AND, OR, NOT, delay elements, synchronization trigger, characterized in that, in order to increase the numbers , and simultaneously synchronized

3 signals varying with a frequency less than a clock frequency, the comparison stage inputs are connected to code buses and command trigger outputs, and its output is connected through the circuit "NOT to one input of stage" AND, the other input of which is connected through two series-connected delay elements with the clock feed bus, and the output of the cascade is “AND connected to the input of the cascade“ OR, the output

5 of which is connected to the input of the installation to “zero of the trigger of synchronization, and the other input through the delay element is connected to the output of the cascade“ And, one input of which is connected to the single output of the synchronization trigger, and the other input through three delay elements connected to the clock supply bus; "Single outputs of the trigger commands are connected to the inputs of the cascade" OR, the output of which is connected to the input

5 cascade "And, the other entrance which through

the delay element is connected to the clock feed pulse bus, and the output is connected to the input of the unit B “a trigger trigger unit; “The zero input of each command trigger is connected to the output of the corresponding cascade“ I, one input of which is connected to the bus, feeds the clock pulses, and the other through the cascade “NOT to the corresponding bus to feed the command code, and“ the single input of each command trigger is connected to the output the corresponding cascade "And, one input of which is connected to the bus clock, and the other - with the corresponding bus feed command code.

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