SU363215A1 - BINARY COUNTER WITH ERROR CONTROL - Google Patents

Description

one

This invention relates to computing and relates to hardware control of digital computing machines.

Known binary counters with error control, containing a counter on triggers, a control trigger and differentiate, and chains.

However, for each controlled discharge of the counter, additional elements are required, which, when the counter is large, greatly complicates the circuit of the counter and increases its dimensions, as well as making it difficult to detect random errors.

The aim of the invention is to increase the reliability of the meter.

The proposed binary counter contains a pulse selector but the duration and pulse shaper. Differentiating chains are connected to the zero outputs of all the triggers and to the unit output of the last meter trigger, the outputs of the differentiating chains are connected and connected via the pulse shaper to the pulse selector input but the duration, one of the outputs to the single inputs of the control trigger. The second single input of the control trigger is connected to the input bus of the meter.

Pa drawing presents a diagram of the proposed counter.

The error counter binary counter consists of triggers /, differentiating chains of resistor 4, driver 5 pulses, selector 6 for duration, delay element 7, control trigger 8, diode 9, coincidence circuit 10.

The control trigger 8 sets the input signal to the state "1.

In the absence of failures, the input signal propagates through the main counting register to the flip-flop /; which is in the "O" position and throws the trigger to

position “1. The voltage drop from the zero output of the In trigger by means of a differentiating chain formed by a capacitor 2p and a common resistor 4 connected through the diode 3p is converted at the input

pulse former 5 in a negative pulse. At the output of the pulse former, a signal is generated with a pulse duration not exceeding the time constant of one differentiating chain. The resulting pulse at the output of the imager passes through the selector 6 for the duration and sets the control trigger 8 to the position “O. Thus, when the counter is correctly triggered, after a certain gap of the Burden, at the end of the input signal, the unit output of the control trigger 8 has a low voltage level. When polling for circuit 10, no error signal is received.

In the case of a counting fault, when the trigger transition from "O to" 1 does not take place at all, the control trigger 8 remains in the "1" position and there is a high voltage level at the single output. When polling from the coincidence circuit 10, an error signal is received.

In case of switching from position "O to position" 1 of two or more flip-flops per input pulse, the capacitors 2 differentiating envelopes of these flip-flops will be parallelized through diodes 3, and at the output of the driver 5 pulses a signal with a pulse duration of two or more times exceeding the time constant of one differentiating chain, that is, its duration is proportional to the number of triggers triggered per input pulse. The selector 6 issues a pulse from the first output and switches the control trigger 8 to the “O” position.

The pulse duration at the input of the selector 6 is longer than the delay time at the delay element 7, at the second output of the selector 6 a pulse appears that switches the control trigger 8 into position "1, and a high voltage level appears at its output. When polling from the coincidence circuit 10, an error signal is received. When the counter triggers are switched from position "1 to position" O, the capacitors 2 of the differentiating circuits are recharged through diodes 9. If the counter overflows by one

The trigger does not switch from position "O to position" 1. In order to eliminate the occurrence of a false error signal from the single output of the trigger of the last bit of the counter, an overflow signal is fed through the differentiating chain to the control circuit.

The use of the proposed counter increases the effectiveness of the control.

Known control schemes provide detection of errors from among single ones - from three faults one, from among double ones - from five faults one.

The proposed counter, however, provides for the detection of errors from among the double ones - out of five errors.

Subject invention

A binary counter with error control, containing the actual counter on the trigger, the control trigger and differentiating chains, characterized in that, in order to improve the reliability of the counter, it contains a pulse selector for duration and pulse shaper, while the differentiating chains are connected to zero output of all triggers and to the single output of the last trigger of the counter, the outputs of the differentiating chains are combined and connected through the pulse shaper to the input of the pulse selector but of duration, one of the outputs of which are connected to zero, and the other to the single inputs of the control trigger, the second single input of which is connected to the input bus of the counter.

Poll

Oa: ibka