SU362489A1 - BACKUP TRIGGER - Google Patents

Description

one

The invention relates to the field of advanced technology and can be used, for example, in memory circuits and registers.

According to the main author. St. No. 276161 known redundant trigger.

A disadvantage of the known redundant trigger lies in its complexity, which leads to high equipment costs for redundancy and reduces its reliability.

In order to simplify and increase the reliability in the proposed redundant trigger, the zero outputs of the trigger arms of all three channels are connected in pairs and connected to the inputs of the first logic modules through the circuit. And the outputs of the first logic modules are also connected in pairs and connected to the inputs of the second logic modules through scheme "OR.

The drawing shows the block diagram of the proposed redundant trigger.

The redundant trigger consists of three channels, each of which contains a two-stage control circuit and two logical modules on AND AND NOT / OR elements. The first stages of the control circuit of the first, second and third channels are formed by elements I-6, respectively, inputs 7-18 of which are fed in pairs by direct information and control. signals. The second stages of the first, second and second control circuit

the third channels are formed by elements 19, 20, and 21, respectively, and inverse control signals are supplied to their inputs 22-27. The first logical modules of the first, second and third channels, respectively, are formed by elements 28-36, and the second logical modules of the first, second and third channels, respectively, by elements 37-42.

The zero outputs of the trigger arms of all three channels are connected in pairs at points 43, 44 and

45, respectively, being the output of the first, second and third channels. In points

46.47 and 48 combined the second inputs of the first logic modules of the first, second and third channels, respectively. The zero outputs of the shoulders of the triggers of the three channels, connected in pairs in points 43, 44 and 45, are connected through the scheme "And connected with the inputs of the first logical modules formed by elements 29 and 30 in the first channel and elements 2 and с35 in the second channel and in the third channel, elements 35 and 36. The outputs of the first logic modules, formed by elements 28, 29 and 36; 30, 31 and

32; 33, 34 and 35 are also connected in pairs and connected to the inputs of the second logic modules formed by elements 37 and 39, respectively; 40 and 41; 38 and 42, through the scheme “OR.

The device works as follows

In the information storage mode (with a valid scheme), the signals at points 46, 47 and 48 are equal to one, and at the outputs of the / 5,20 and 21 elements - zero, since the control signals are equal to zero, while the information stored at the trigger outputs, inverted by elements 29 and 30; 32 and 33; 35 and 36 and is fed to the inputs of the elements 37-42, with the result that a stable state of the device is achieved.

In the information recording mode (with a valid circuit), the inverted values of the control signals are supplied to the inputs 22-27, three of which are equal to one, and the inputs of the elements -6 are the direct values of the information and control signals, while at the zero outputs of the arms The triggers of the three channels are set to the information "111 or" 000, inverse to the information supplied to the input from the corresponding recording direction. After all control signals become equal to zero, the information is memorized.

When an error of the type "open-circuit at the input of one of the trigger channels" occurs, the zero shoulder of this trigger is actually replaced with the zero shoulder of the neighboring trigger combined with this one, as a result of which the error is corrected.

When a type of fault appears, a short circuit at the input of one of the trigger channels on the zero arm of the given trigger and zero arm of the trigger connected to this one, temporarily appears false; since the unit arm of this trigger is combined according to the “OR with the adjacent channel, and the output of the malfunctioning arm is zero, information is corrected on the unit arm of this trigger, which, in turn, neutralizes the effect of the false unit at the input of the zero arm of this trigger, and the correct information is also set at its output. The recording time of the information in this case is increased by an amount equal to the propagation delay of the signal in the two channels.

Subject invention

Redundant trigger on auth. St. No. 276161, characterized in that, in order to simplify and increase reliability, the zero outputs of the trigger arms of all three channels are connected in pairs and connected to the inputs of the first logic modules through an AND circuit, and the outputs of the first logic modules are also connected in pairs and connected to the inputs of the second logical modules through the OR circuit.