SU1742817A1 - Polar coordinate converter - Google Patents

Abstract

The invention relates to computing, is intended to form codes of rectangular coordinates of a circular scan with programmable beginning and length, and codes of rectangular coordinates familiarity of characters with programmable dimensions and can be used in the construction of a functionally oriented control processor of a vector display or raster electron beam display device information display complex information system such as weather radar. The purpose of the invention is to expand the functionality of the converter by allowing the redefinition of the beginning and length of the circular scan and the possibility of forming the rectangular coordinates codes of familiarity of symbols while simplifying the converter. New is that the converter contains the second, third, fourth AND elements, the decoder of control signals, five AND-NOT elements, the fourth register, the second and third counters, the third and fourth combinational adders, the first block of AND elements and the fifth element And, contained in the first functional block, the second block of elements And, and the sixth element And, contained in the second functional block, 3 Il. O w fe

Description

The invention relates to the field of computer technology, is intended to form the codes of rectangular coordinates of a circular scan with programmable beginning and length and codes of rectangular coordinates familiarity with the secondary information symbols and can be used in the construction of a functionally oriented processor (FOP) control vector or raster (television) electronic -beam indicator of a device for displaying information (CID) of a complex information system such as a weather radar (MRL).

In the structure of the UOI of a modern MRL, you can select an indicator on an electron-beam device (EBU) with two-coordinate electromagnetic control of the position of the beam (or rays) of the electronic signature and modulation in brightness and (or) color, keyboard control of the modes of operation of the IC, marker coordinate sensor, generate codograms operator and FOP to connect the SPI with other subsystems of the IRL and to control the indicator in the process of synthesizing the information model of the situation in the area of view of the IRL;

l

S 00

VI

an input / output device, an analog-to-analogue indicator control signal generator, an on-line memory of code information (azimuth code of the position of the MRL antenna in azimuth, operator codogram codes, secondary information codogram codes, etc.), function generator for generating the codes of the required constants and sine, cosine, arctangent and arc-tangent functions, a microprocessor to perform all the required arithmetic and logical operations, a character generator, this polar coordinate converter, a device GUT program control, the device synchronization and time programs, the device simulation and control and data bus (SD), address (IRA) and a control (CC).

In the CID of a modern MRL, both primary and secondary information is displayed, most of which are formulas for the results of processing primary information, and each of the formulas consists of one or several symbols. In this connection, in order to build a modern EIS in the composition of the FOP, a converter is needed to form the codes of the rectangular coordinates of both the circular scan to display the primary information and familiarity of the symbols to display the formulas of the secondary information.

A device for converting polar coordinate codes of a circular scan or coordinate point into codes of rectangular coordinates is known, and contains three registers, a counter, two triggers, a sine function generator, a multiplier, four OR elements, five AND elements, two NOT elements, two elements OR-NOT, element NAND, inputs of angle and range codes, start inputs, mode control, pulse number range code, clock input and outputs of direct codes of rectangular coordinates of a circular scan or a coordinate point.

The drawbacks of the device are the limited functionality (there is no possibility of programming initial rectangular sweep coordinates and the possibility of forming codes of rectangular coordinates familiarity with the secondary information symbols) and complexity due to the construction of this device without taking into account the functionality of other FOP devices of a modern EOI.

The most / see close to the technical essence of the proposed is a radial-circular scanning driver

for a circular view indicator containing a sensor (register) (2 + n) -discharge angle code, range code counter, trigger, AND element, sine and cosine function generator, formed by the NOT element, two blocks of controlled inverters, EXCLUSIVE OR and two memory blocks, each of which is programmed to play an n-bit sine code to a pop-bit angle code belonging to the half-interval 0 °, 90 °, two accumulating adders, a clock generator, the start input and the outgoing direct rectangular codes coordinate inat

5 circular scan.

The drawback of the device lies in the fact that it, with significant hardware costs, has limited functionality (there is no possibility

0 programming of the beginning and length of the circular scan and the possibility of forming the codes of the rectangular coordinates of the familiarity of the symbols of the secondary information), due to the construction of this

5 devices without taking into account the functionality of other devices FOP modern UOI.

The purpose of the invention is to expand the functionality of the converter by allowing the redefinition of the beginning and length of the circular sweep and the ability to form codes of rectangular coordinates for familiarity of symbols while simplifying

5 converter.

Figures 1 and 2 illustrate the functional diagram of the polar coordinate transducer; on fig.Z - timing diagrams, showing the work of the converter in

0 time in the process of the functioning of the OID.

The converter (Fig. 1) contains the first 1, second 2, third 3 and fourth 4 elements And, the first 5 and second 6 function blocks, the first 7, second 8 and third 9 counters, the decoder 10 control signals, the first 11, the second 12, third 13, fourth 14 and fifth 15 elements AND –NE, trigger 16, third 17 and fourth 18 registers, third 19 and fourth 20 combiner adders, first 21 and second 22 inputs of the installation connected to the first inputs of the first 1 and the second 2 elements And, respectively, the first 23 and second 24 inputs of impulses of changes in the familiarity of the symbol by the first and a second rectangular coordinates connected to the first inputs of the third and fourth 3 and 4 elements, respectively, the input transducer 25 mode signal, a clock input

26 connected to the gate input of the decoder 10 and the reset input of the trigger 16, the start input 27, the clock input 28, the write control input 29 connected to the information decoder input 10 and the information (2 + n) data discharge input 30 connected to the inputs parallel recording of counters 7-9 and information inputs of registers 17 and 18, outputs 31-35 of decoder 10, the first 31 outputs of which are connected to the second inputs of the first 1 and second 2 And elements and the write input of the second counter 8, the overflow output of the first counter 7 is connected to clock input 16, the second output 32 of the decoder 10 is connected to the recording input of the third counter 9, the third 33, the fourth 34 and the fifth 35 outputs of the decoder 10 are connected to the synchronization inputs of the third register 17, the fourth register 18 and the write input of the first counter 7, respectively, direct the output of the trigger 16 is the output of the signal of the mode of forming the codes of the rectangular coordinates of the circular scan of the converter, the first 5 (or second 6) block (FIG. 2) containing the first 36 (or second 36) block of elements And, the fifth 37 (or the sixth 37 ) element And, the first 38 (or the second 38) combinational adder and the first 39 (or second 39) register, while the low-order outputs of the first and second combinational adders 38 are connected respectively to the information inputs of the first and second registers 39, the outputs of which are connected to the inputs of the first components of the first and second combinational adders 38, the input 25 of the signal mode is connected to the first inputs of the elements of the first and second blocks 36 and the first inputs of the fifth and sixth elements And 37, the outputs of the first 1 and third 3 elements And connected respectively With the reset input and the synchronization input of the first register 39, the outputs of the second 2 and fourth 4 elements I are connected respectively to the reset input and the synchronization input of the second register 39, the installation inputs of the first and second registers 39 and trigger 16 are connected to the start input 27, the information outputs The third and 17 registers of the 18 registers are connected to the inputs of the second terms of the first and second combinational adders 38, respectively; the high-order output of the first combinational adder 38 is connected to the second input the fourth element And 37 and the first inputs of the first 11 and second 12 elements of the NAND, the output of the senior bit of the second combiner 38 is connected to the second

the input of the sixth element AND 37 and the first inputs of the third 13 and fourth 14 elements AND-NOT, the input of the sign bit of the third register 17 is connected to the second inverse 5 input of the first 11 and the second direct input of the second 12 elements AND-NOT, the output of the sign bit of the fourth register 18 is connected to the second inverse of the third input 13 and the second direct input of the fourth 14 non-IS elements, the clock input 28 of the converter is connected to the first input of the fifth IS 15 element, the output of which is connected to the subtracting input of the first counter 7, trigger output 16 is connected to torym

5 input of the fifth element AND-NOT 15, the output of which is connected to the second inputs of the third 3 and fourth 4 elements AND and the inverse third inputs of the elements AND-NOT from the first 11 to the fourth 14, outputs

0 of the first 11 and second 12 elements of the IS-NOT are connected respectively to the summing and subtractive inputs of the second counter 8, the outputs of the third 13 and fourth 14 elements of the IS-NOT are connected respectively to the summing and subtractive inputs of the third counter 9, the outputs of the second 8 and third 9 counters connected to the inputs of the first components, respectively, of the third 19 and fourth 20 combinational adders,

0 inputs of the second addend which are connected to the outputs of the elements And, respectively, the first and second blocks 36, the outputs of the third 19 and fourth 20 combinational adders connected to the outputs, respectively

5 of the first and second results of the converter, the input of the logical zero of which is connected to the information input of the trigger 16, the carry inputs and the senior bits of the second terms of all four combination adders 38, 19 and 20.

The Converter (Fig.1 and 2) is made for p 10 on integrated circuits (IC) series 533 so that each of the counters 7 (or 8, or 9) contains three And C 533 and IE7,

5, the register 17 (or 18) is made on two ICs 533 TM9, the adder 19 (or 20) is executed on three ICs 533 IM6, the decoder 10 is the IC 533 ID7. trigger 16 is made on half of IC 533 TM2, adder 38 is implemented on three IC 533 IM6, register 39 is executed on half of IC 533 TM2 and two IC 533 TM9, and elements 1-4 and 11-15 of the converter and elements of block 36 and element 37 block 5 (or 6) are made on combinational

5 elements of the corresponding IC of the 533 series. At the inputs and outputs, the converter and its component parts are denoted by F. P and I (or I), respectively, codes, potential signals and forward (or inverse) pulses so that after each of these letters

is the number of the generator input or the number of the output of its component part, or the number of the component of the generator, for example, FZO - code at input 30, D25 - potential signal at input 25, I26 - inverse pulse at input 26, I28 - forward pulses at input 28, F17 is the code at the code output of register 17, P17 is the potential signal at the output of the sign bit of register 17, I1 is the inverse pulse at the output of element 1.

It should be noted in the vice that the trigger 16 directly on I26 (on I27) is set to O (to 1), and after the completion of the overflow pulse I7 to subtract counter 7, the trigger 16 is set to O, the asynchronous insertion of the corresponding codes (above the slash line that intersects the code converter busbars (Figures 1 and 2), the digits of these codes are put in parentheses) in counters 7-9 are made directly for the action of I35, I31 and I32 pulses, respectively, the register 39 is directly set to F39,000 ... O and ... (or 6) is produced by I1 (or I2) and I27, respectively, the synchronous recording of the corresponding codes in registers 17 and 18 is made at the end of the IZZ and I34 pulses, respectively, the synchronous recording of the code in the register 39 of block 5 (or 6) is carried out at the end of each pulse FROM (or I4), synchronous reduction of the contents of counter 7 is performed with the end of each pulse I15, and synchronous increase (or decrease) of the contents of counters 8 and 9 is made with the termination of pulses I11 (or I12) and I13 (or I14), respectively.

Temporary programs of formation of input codes and converter signals (codes F29 and FZO, belonging to ША and ШД FOOL, respectively, and accompanied by synchronization pulses И26 of data recording, belonging to ШУ FOP. Which belong to the first И21 and second И22 1 pulses of the generator setup, the first И23 and the second И24 pulses of changes familiarity of the symbol by the first and second rectangular coordinates, respectively; the converter mode signal P25, the generator start pulse 27 and the clock pulses E28) determine the time programs of the forms its audio output codes F19 and F20, so that the following four modes (fig.Z) can be isolated in generator operation: a first mode of duration T1 - preparation mode to the formation codes rectangular coordinate circular sweep with programmable start and length; the second mode, duration T2, is the mode of forming the codes of the rectangular coordinates of the circular scan; the third mode with the duration of the TZ is the mode of preparation for the formation of codes for rectangular coordinates of familiarity of characters with programmable dimensions of familiarity in both coordinates; the fourth mode with T4 duration - the mode of forming the codes of rectangular coordinates familiarity

0 characters.

The alternation of the operating modes of the converter is ensured by the mutual synchronization of its input signals and codes, i.e. software control devices

5 synchronization and time programs FOP, and is carried out so that after each first mode follows the second mode, after each second mode can follow the first or third mode, after

0 each third mode can be followed only by the fourth mode, and after the fourth mode the first or third mode can follow, for example, FIG. 3 shows the sequence of modes: T1 - T2 - TK - T4 5 TK -....

The decoder 10 serves to generate recording pulses into the converter of the corresponding FZO codes from pulses I26 and code F29 as follows. With

0 Ф29 001 according to И26, a pulse I31 is written to record the modified additional code FZO Xn of the first (vertical) rectangular coordinate or the beginning of a circular scan in the first mode, or the first familiarity of the secondary information formula symbol in the third mode, except for Goy, I31 are generated pulses I1 and I2, which establish registers 39 of blocks 5 and 6 in O. At F29 010 and I26, I32 records the modified additional code FZO YH of the second (horizontal) coordinate or the beginning of a circular scan in the first mode in the third mode, the first

5 familiarity symbol of secondary information formulas. 011 through I26, a pulse of OZZ writing to the register 17 of the FZO code is formed, which is in the first mode the forward cosine code of the azimuth A of the antenna,

0 ie FZO cos A KOK1 ... Kp, where KO is the bit of the digit O or 1m of the digit bit of this code, and in the third mode, the FZO Xc positive code is the size of the familiarity of the symbol in the first right-angled coordinate. With F29 100 and I26, an impulse I34 is written to write into register 18 of the FZO code, which in the first mode is a direct sine code of azimuth A of the antenna, i.e. FZO sm A COC1 ... Cn, where CO is the bottom digit of the sign bit of this

code, and in the third mode, the positive FZO code, YC, the size of the familiarity of the symbol on the second rectangular coordinate. At Ф29 101 according to И26, an impulse И35Л Records is formed in counter 7 of the FZO code g5p - 2 n, where 0 ... 01, and br is the code of the length (duration) of the circular scan, varying with a quantum from Гп to 1-2 п, where Т - 01.0 ... О - modified additional code of the number + G.

Counter 7, item 15 and trigger | 16 serve to generate pulses I15 A16 I28, representing the result of the operation of converting a binary parallel code Dp, recorded in the first mode into counter 7 through I35 as a parallel code dp - 2 liters, into a pulse number code representing T2 the second mode, the pulse sequence I15 (in the second mode IZ I4 YT5), the number of pulses in which is

Chi15 Chiz-Chi4 2P. Dp 2P U DI -2N, (1)

eleven

where DI is the bit digit of the i-ro (I 1, n) bit code br.

Elements 1 and 2 are used to form pulses I1 I21 V I31 and I2 I22U VM31 of the installation in O of registers 39 blocks 5 and 6 through the first inputs of the installation, respectively.

Elements 4 are used to form pulses FROM I23 V I15 and I4 I24U I15 clock (synchronous) writing codes P37F38 in the registers 39 of blocks 5 and 6.

Register 17 (or 18) is used for storing in the first and second modes of the direct code P17F17 KOK1 ... Kp cosine (or P18F18 COC1 ... Cine sine) antenna azimuth, and in the third and fourth modes of the positive code F17 Xc (or Ф18 Yc) the size of the familiarity of the symbol by the first (or second) rectangular coordinate.

Block 5 (or 6) in the second mode (at the beginning of this mode, the register 39 by the pulse H27 is set to the state Ф29 010 ..., 5) performs the operation of multiplying the binary n-code code Ф17 Icds AI К1 ... Кп ( or F18 I stn A | C1 ... Cn) to the binary n-bit code D (t), which varies from 0 to o p during T2 and is represented on the clock inputs of registers 39 by the number-pulse code, t. a sequence of pulses FROM I15 (or I4 YT5), whose number of pulses during T2 varies from 0 to (1).

During T2, the results of multiplication operations, performed by blocks 5 and 6, are

battled in the form of numbers г and Ч of their overflows, i.e. Equality numbers (1) of signals П5 and ПБ respectively, according to the algorithm

/ 4n5 (t) -IcosAJ -Y. J4ri6 ent 4D (t) - | sfn A | + 0.5,

(2)

where ent is the operation of separating the integer part of the number enclosed in square brackets;

4o (t) is the number of pulses I15 determining the current scan code of the range during T2, i.e. D (t) Cho.

The results of multiply operations (2) are generated in number-pulse codes, i.e. the numbers of unit values of the adders 38 are blocks 5 and 6, with the weight of each pulse, and the error of each of the multiplication operations (2) is distributed approximately according to the law of equal probability with a zero mathematical expectation.

Blocks 5 and 6 during the fourth mode (only in this mode, the signal P25 1) with the signal house P25 1 and pulses FROM I23 and I4 I24 produce codes

 F5 Xc-Cheese; Fb c-cheech

(3)

thirty

35

40

45

50

55

changes in the rectangular coordinates of the familiarity of the symbol relative to the initial (first) familiarity (Xn, Un, where Chiz (or Fr) is the number of pulses of the ITT I23 (or I4 I24) changes in the familiarity at the first (or second) rectangular coordinate received at the synchronizing input of the register 39 block 6) after zeroing its register 39 for I1 (or I2) .A

Codes (3) may not be equal to 0 only during the fourth period, during which each of them can change only from 0 and can take the value up to (2–2), since the signal P25 1, i.e. during the duration T4 of the fourth mode, the passage of the high bit of the adder 38 to the input of the high bit of register 39 and the passing of the F39 code of the register 39 to the output of block 36, i.e. generation of the FZb F39 code, in which the most significant bit has a weight of 2 °, and the youngest one has a weight of 2.

Elements 11 and 12 (or 13 and 14) are used to form pulses I11 - I15-CO-P5II 12 I15-KOP5 (or I13 I15-CO-P6 and I14 I15 and CO P6) of the positive and negative pulse number code of the first (or second) ) from works (2) with the weight of each pulse 2 and respectively.

Counters 8 and 9 serve in the first mode (or in the third and fourth modes) for

receiving and storing additional modified codes of rectangular coordinates, i.e. Ф8 & and Ф9 YH, respectively, the beginning of the circular scan (or the first familiarity of the symbol of the secondary information formula), and in the second mode to form additional modified codes of the rectangular coordinates of the circular scan according to the expressions

to

i-n

(Ф8 Хн + НГ ЧИ ХН + АХ «Хн + Щт.) -Cos А;

FN-UU + Hf0 YH + AY “v; + D (t) sin A.

 : .-: o CHP6 “2; P

Adders 19 and 20 serve to form the output codes of the converter.

Ф19 Ф8 + Ф5; Ф20 Ф9 + Ф6.

which are modified additional codes of rectangular coordinates or circular scan in the second mode or familiarity of the symbol in the fourth mode.

The operation of the converter as a whole, starting, for example, from the first mode, can be described as follows.

In the operation of the converter in each first mode, two parts can be distinguished, in the first of which, five sequences of F29 and FZO codes go to the converter, followed by a sequence of five I26 pulses, with which the decoder 10 generates a sequence of I31, I32 pulses. IZZ, I34. And 35. and on I31, I1 I31 and I2 I31 are formed (Fig. 3a, dl). As a result, after the end of the first part of the first mode, the following codes are contained in the converter: Ф8 - U, Ф9, П17Ф17 КОК1 ... Кп, П18Ф18 СОС1 ... Sp, Ф395 Ф39е 00 ... О, Ф7 Dp - 2. During the second part of the first mode by the duration of the Log no changes occur in the converter and it waits for the second mode to start.

Each second generator mode starts on the start pulse I27 (in time this pulse does not coincide with any of the pulses I28), which sets the trigger 16 to T (in this state, the trigger 16 produces a signal A16 1), and the registers 39 of blocks 5 and 6 on I27, they are set to F395 - 010 ... O and F39b - 010 ... O 0.5, respectively. During the time T2 of the second mode (Fig.Zm-p), the element 15 produces

after that, I have a pulse I15 P16-I28 pulse number code of the current range D (t), the number of pulses in which is defined by formula (1). By pulses I15

5, elements 3 and 4 form pulses FROM I15 and I4 I15, with which blocks 5 and 6 function according to (2), counters 8 and 9 using elements 11-14 function according to (4) due to the fact that at the end

10 of each pulse E11 or I12 (or I13 or I14) the contents of counter 8 (or 9) are increased or decreased by one quantum. As a result, modified additional (4) codes (t) & + AX (t) and Ф20 Y (t) YH + (t) of the current rectangular coordinates X (t) and Y (t) of the circular scan, the variable components of which AX D (t) cos A

20 and A Y D (t) sin A simulate the rectangular coordinates of the position in space (5) of the architecting beam of the MRL antenna. Ends second mode with the end of the pulse I7 overflow on the subtraction of the counter

25 7 (with the end of each I15, the content of the counter 7 is reduced by) setting the trigger 16 to the state O, in which the trigger 16 generates a signal A16 O prohibiting the operation of the element 15.

30 During the operation of the converter in every third mode, two parts can be distinguished, in the first of which four time sequences of F29 and FZO codes are sent to the converter,

35 followed by a sequence of four pulses I26, with which the decoder 10 generates a sequence of pulses I31, I32, IZZ. I34, and I31 forms I1 I31 and I2 I31

40 (Fig.3a, dz, k, l). As a result, after the end of the first part of the third mode, the registers 39 of the blocks 5 and 6 are set to Ј, the counters 8 and 9 contain the codes Ф8 Хн and Ф9 of the initial (first) character familiarity

45 formulas of secondary information, and registers 17 and 18 contain the codes F17 Xc and F18 YC of the size of the familiarity of the symbol by the first and second rectangular coordinates, respectively. During the second part, the third 50 of its mode with the duration TZozh no changes in the converter occurs and he waits for the start of the fourth mode.

For definiteness, we describe the operation of the converter in the fourth mode with

55 generating codes for rectangular coordinates of familiarity of characters, for example, / eight-bit formula, displaying two characters of four characters / each line in two lines.

Every fourth mode starts with the arrival of a P25 1 signal converter, which allows the converter to operate according to expressions (5), in which the variables are the F5 Xc Chiz codes and F6 Yc Chi4 rectangular coordinates of the symbol character within the formulas.

In the fourth mode on modified additional codes F19 X - $ n + & Chiz and F20 U + VV Ch4 of the rectangular X and Y coordinates of each familiarity of the formula symbol in the FOP is performed using the symbol generator of the operation of the sweep of the codes of the rectangular coordinates of the symbol within a part of its familiarity. As a result, the symbol is displayed in the vector WOS, and the content of the corresponding cells of the raster RAM of the secondary information of the D / A indicator indicator control signal is updated in the raster WI.

After performing each such operation in the FOP in each line of the formula, besides the last performed at the last extreme place in each line, the converter receives an impulse I24, which is used to generate the impulse I4J124, increasing by Yc the contents of the register 39 of block 6, whereby the converter generates the codes (5) of the next character familiarity in this line of the formula, and when this operation is completed in the FOP, the last (extreme) character of the character (in the described case on the fourth, fig.3b, c, d l, m, n, c) in any line of forms At the same time, I / I23 pulses arrive at the converter (I1G I22 and IZ I23 pulses are generated by it), by which the contents of register 39 of block 5 are increased by Xc, register 39 of block 6 is set to O and the converter generates codes (5) the rectangular coordinates of the first character in the next (upper) line of the formula. At the end of the FOP operation, sweep the codes of the rectangular coordinates of the symbol within the part of the last familiarity of the converter formulas, the next pulses I22 and I23 arrive, after which the signal P25 0 and the generator goes into operation, for example, in the third mode, etc. .

Claims (1)

The technical and economic efficiency of the proposed converter lies in the fact that it is simpler than the known one and in comparison with it possesses significantly broader functional capabilities due to the possibility of programming the beginning and length of the circular scan and the possibility of generating codes of rectangular coordinates of familiarity of characters with programmable familiarity dimensions. both coordinates. Claims of the polar coordinate converter containing two combinational adders, the first counter, three registers, the trigger, the first element I, and the trigger input of the converter is connected to the trigger setup input, the clock input of which is connected to the first counter overflow output, The second combinational adders are connected to the information inputs of the first and second registers, respectively, the outputs of which are connected to the inputs of the first components of the first and second, respectively combinational adders, the output of the trigger is connected to the output of the signal for generating the codes of the rectangular coordinates of the circular scan of the converter, characterized in that, in order to extend the functionality by providing the possibility of redefining the beginning and length of the circular sweep and the possibility of forming the codes of the rectangular coordinates, the symbol with the simultaneous simplification of the converter, it additionally contains two counters, a control decoder, two combinational adders a, two blocks of elements And, the fourth register, five elements And, and the input of the operand of the generator is connected to the inputs of parallel recording of counters from the first to the third and information inputs of the third and fourth registers, the first and second inputs of the converter installation are connected to the first inputs of the first and The second And elements, the first and second inputs of the inverter symbol familiarity changes of the converter are connected to the first inputs of the third and fourth And elements, respectively; the converter mode input En with the first inputs of the elements of the first and second blocks and the first inputs of the fifth and sixth elements of AND, the recording control input of the converter is connected to the information input of the control decoder, the synchronization input of the converter is connected to the input of the decoder gating and the trigger reset input, the first output the control signal decoder is connected to the second inputs of the first and second elements And and the recording input of the second counter; the second output of the control signals decoder is connected to the synchronizing signal the third counter, the third and fourth outputs of the control decoder are connected to the clock inputs of the third and fourth registers, respectively; the fifth output of the control decoder signals are connected to the write input of the first counter; the outputs of the first and third elements And are connected respectively to the reset input and the clock the input of the first register, the outputs of the second and fourth elements And are connected respectively to the reset input and the synchronizing input of the second register, the installation inputs The first and second registers are connected to the trigger input of the converter, the outputs of the information bits of the third and fourth registers are connected to the inputs of the second term, respectively, of the First and Second Combined Sum-Toors, whose higher bits are connected to the second inputs of the fifth and sixth elements, respectively; which are connected to the inputs of the higher bits, respectively, of the first and second registers, the outputs of the higher bits of the first and second combinational, adders are connected to the first inputs n the first, second, and third, fourth, and NAND elements, respectively, the output of the sign bit of the third register is connected to the second inverse of the first and second direct input of the second AND element, the output of the sign bit of the fourth register is connected to the second inverse of the third and second by the direct input of the fourth NAND element, the clock input of the generator is connected to the first input of the fifth NAND element, the output of which is connected to the subtractive input of the first counter, the output of the trigger is connected to the second input of the fifth NAND element, you od which connected to the second inputs of the third and fourth elements AND, inverse third inputs of the elements AND NES from the first to the fourth, the outputs of the first and second elements NAND are connected respectively to summing and subtractive inputs of the second counter, the outputs of the third and fourth elements AND-NOT are connected respectively to the summing and subtracting inputs of the third counter outputs of the second and the third counters are connected to the inputs of the first components of the third and fourth combinational adders, respectively, the inputs of the second component of which are connected to the outputs of the elements And, respectively the first and second blocks, the outputs of the third and fourth combinational adders are connected to the outputs of the first and second results of the converter, respectively, the input of which is the logical zero connected to the information input of the trigger, the inputs of the transfer of combinational adders from the first to the fourth and the inputs of the senior bits of the first and second combinational adders. (2 + p.) 1