SU1742691A1 - Analyzer of silicon contents in liquid pig iron - Google Patents

Abstract

Usage: in ferrous metallurgy and foundry industry for operational silicon content in molten iron. SUMMARY OF THE INVENTION: To provide an automatic input to the readings of a phosphorus correction device in the melt, which improves the accuracy of determining the silicon content based on the solidus temperature and expanding the application area of the device. Digital analyzer contains interconnected analog-digital converter, threshold counter, first buffer counter, time counter, first binary multiplier, second binary multiplier, result counter, second buffer counter, phosphorus count sensor, first zero decoder, second decoder zero, trigger , the first element And, the second element And, the element OR, and the block of digital display.

Description

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The invention relates to computing and can be used in ferrous metallurgy and foundry for rapid analysis of the silicon content in molten iron according to the cooling curve of its sample.

A device is known for determining the silicon content in liquid iron from a cooling curve, comprising an interconnected temperature sensor, an analog-digital converter, a pulse generator, a synchronization unit, a time counter, a discriminator of local increments, three reversible counters, a trigger and logic elements AND, OR, NOT. This device provides the determination of the silicon content in the melt by automatically processing the sample cooling curve (thermogram) and detecting

there are peculiar anomalous areas (temperature pads) arising at liquidus temperatures (onset of crystallization) and solidus (crystallization termination) due to the exothermic effects of phase transformations. However, this device is operable only in those cases when distinct liquid horizontal temperature sites are not observed at the liquidus and solidus temperatures on the cooling curve, which narrows the field of application of the device.

The closest to the claimed technical entity is a device that contains an analog-to-digital converter, whose input is the device input, a threshold counter, the addition and subtraction inputs of which are connected to the first and second code pulses anvl

four

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a logo-digital converter, the first clock output of which is connected to the counting input of the first time counter and the first input of the first element AND, the output of which is connected to the input of the second time counter, the intermediate overflow output of which is connected to the first input of the OR element, the overheating counter and the first trigger, the input of which is connected to the output of the overheating counter, and the output to the second input of the first element I, the first overflow output of the threshold counter is connected to the first inputs of the initial installation of the first and The second time counter, the second overflow output of the threshold counter is connected to the input of the overheating counter, the second input of the first time counter, the first input of the second trigger and the first input of the second element, the second input of which is connected to the second input of the initial trigger. setting the second time counter, the intermediate overflow output of the first time counter is connected to the second input of the second trigger and the initial installation input of the overheating counter, the second output of which is under The key is connected to the first input of the third element AND, the overflow output of the first time counter is connected to the input of the third trigger and the second input of the OR element, three digital display units whose outputs are device outputs, three binary multipliers, three result counters, fourth and fifth elements AND , a buffer counter and a zero decoder, the input of which is connected to the output of the buffer counter, whose information input is connected to the output of the parallel code of the analog-to-digital converter, and the control input - to the output of the AND input LI, the overflow output of the second time counter is connected to the second input of the third element I and the first input of the fourth element I, the second input of which is connected to the second output of the clock pulses of the analog-digital converter, the third input is connected to the output of the decoder zero, and the output of the fourth element And connected to the counting input of the buffer counter and the inputs of the first, second, and third binary multipliers, the output of the first binary multiplier is connected to the input of the first result counter, the output of which is connected to the input of the first digital display unit, the outputs of the second binary multiplier are connected to the inputs of the subtraction and subtraction of the second result counter, the output of which is connected to the input of the second digital display unit, the outputs of the third binary

the multiplier is connected to the inputs of the addition and subtraction of the third result counter, the output of which is connected to the input of the third digital display unit, the output of the third

the trigger is connected to the first input of the fifth element I, the output of the third element and is connected with the second input of the fifth element I, the blocking input of the overheating counter, the control input of the first digital display unit and the control inputs of the first, second and third binary multipliers, and the output of the fifth element And is connected to the control inputs of the second and third digital display units

This device allows a high degree of reliability to carry out the processing of thermograms in which the anomalous portion appearing at the liquidus temperature has the form of an inclined temperature

site, which expands the scope of the device.

During the crystallization of the so-called hypereutectic cast irons, in particular during the crystallization of high carbon content blast furnace irons, at the liquidus temperature, neither the horizontal nor the inclined temperature of the site can be observed. Naturally, in such cases, the prototype will not be able to determine

liquidus temperature, and therefore the determination of the silicon content in zazhtektichesky cast iron using a known device is possible only by the temperature of the solidus in accordance with the expression

Si Ko-KiTs, (1)

where Si is the percentage of silicon in the sample; Ts is the solidus temperature, Ko, Ki are constant coefficients.

However, it is known that not only silicon, but also other alloying elements of the melt affect the temperature of the solidus temperature Ts. Thus, in particular, phosphorus has about four times more influence on the value of Ts than silicon.

Consequently, the use of a known device for analyzing the percentage of silicon in hypereutectic cast irons is inevitably accompanied by considerable errors due to possible known phosphorus contents in the melt during long service life.

which significantly reduces the use of the device.

The aim of the invention is to improve the accuracy of the analysis and expand the use of the analyzer.

This goal is achieved in that the silicon content analyzer in molten iron contains an analog-digital converter whose input is a device input, a threshold counter, the addition and subtraction inputs of which are connected respectively to the first and second outputs of the analog-digital converter, the first buffer counter, information input of which is connected to the third output of the analog-digital converter, time counter, the counting input of which is connected to the fourth output of the analog-digital conversion bodies, and the inputs of the initial installation of the time counter are connected to the overflow outputs of the threshold counter, the first element AND, the first input of which is connected to the fifth output of the analog-digital converter, the first binary multiplier and the first decoder zero, the information input of which is associated with the outputs of the bits the first buffer counter, and the output is connected to the second input of the first element I, the output of which is connected to the subtraction input of the first buffer counter and the input of the first binary multiplier, the second binary multiplier, the counter the result and the digital display unit, the output of which is the output of the device, the information input of the digital display unit is connected to the outputs of the bits of the result counter, the trigger, the OR element and the second AND element, the first input of which is connected to the trigger output, and the overflow output of the counter time is connected to the first input of the trigger and to the control input of the first buffer counter, contains a master, a second decoder zero and a second buffer counter, the input of which is subtracted to the output of the second binary multiplier, infor The sensor's output output is connected to the information input of the second buffer counter, the first input of the OR element is connected to the output of the first binary multiplier, and the output of the OR element is connected to the subtraction input of the result counter, the information input of the second decoder zero is connected (the outputs of the bits of the second buffer counter, and the output of the zero decoder is connected to the control input of the digital display unit and the second input of the second element I, the third input of which is connected to the fourth output of the analog-digital converter, and the output is connected to the second input of the OR element and the input of the second binary multiplier, the sixth output of the analog-digital converter is connected to the control inputs of the result counter and the second

buffer counter, as well as to the second input of the trigger.

FIG. 1 shows the scheme of the claimed device; in fig. 2 - the circuit of the constructor; 5 nor analog-digital converter; in fig. 3 is a timing diagram explaining the principle of operation of the device.

The proposed analyzer for the content of silicon in liquid iron contains an analog digital converter 1, a threshold counter 2. first buffer counter 3, counter 4 times, first binary 5, second binary multiplier 6, counter 7 of the result, second buffer counter 8, setpoint 9,

5, the first decoder 10 is zero, the second is decoder 11 is zero, trigger 12, the first element is AND 13, the second element is AND 14, the element OR 14 and the digital display unit 16. In this case, the result counter 7 and the second buffer

0, the counter 8 is a binary decimal pulse counter, and the counter 4 time, the threshold counter 2 and the first buffer counter 3 are binary pulse counters.

5 Setpoint 9 is a group of switches by means of which, before the beginning of the next analysis cycle, the binary-decimal code of the tenth and hundredth fractions of the percentage of phosphorus P in the analyzed sample is established. Typically, for the foundry and blast furnace production, the phosphorus content in the cast iron changes relatively little during the day of operation of the unit and, therefore,

5 is known to the technologist in advance at the time of the next analysis of the silicon content. By means of setpoint switches 9, the installed inputs of the corresponding bits of the binary-decimal buffer

0, the counter 8 is connected to the bus of the logical unit or in the bus of the logical zero of the device.

So, for example, if the phosphorus content in the analyzed sample is 0.15% P,

5 then the binary code set by the setting device 9 is equal to Мr 0001 0101. Therefore, in this case, using the setting switch 9, you need to connect the first and third bits of the first decade and the first bit of the second decade of the buffer counter 8 to the bus of the logical unit, and the remaining bits connect to the bus logical zero.

The invented device provides

5, automatic determination of the silicon content of Si in the melt by the solidus temperature Ts with correction by the value of the phosphorus content of P. The calculation of Si is carried out in accordance with the equation of regression and

SI-Ko-KiTs-, K2P,

(2)

wherein the constant coefficients Co, KI, Kg are determined based on the least squares method based on the results of the control analyzes. In this case, the constant coefficient K is set at the installation inputs of the binary-decimal counter 7 of the result, and the coefficients KI and Kg are set with the help of binary multipliers 5 and 6, respectively.

For example, if the coefficient Co is equal to 2.96 (binary-decimal code 0010 1001 0110), then in this case the installation inputs of the second and third bits of the first decade, the first and fourth bits of the second decade, and the second bit of the third decade are binary - the virtual counter 7 of the result must be connected to the bus of the logical unit of the device, and the installation inputs of the remaining bits of this counter must be connected to the bus of the logical zero.

The scheme of the device claimed takes into account the fact that the coefficient Ki in equation (2) is always less than one, and the coefficient Kg is always greater than one. Therefore, the order of installation of these coefficients is different and consists in the following.

To set the KI coefficient on the input inputs of the binary multiplier 5, a binary code of the value N is established, which is related to the coefficient Ki and the size M of the binary multiplier 5 by the relation

Ni 2M / K.

(3)

So, for example, if KI is 0.566 and the binary multiplier is 5-bit (M 9), then in accordance with (3) the value of NI is approximately equal to 290 (binary code 100100010). Therefore, in this case, the switches of the second, sixth, and ninth bits of binary multiplier 5 must be connected to the bus of the logical unit of the device, and the rest to. bus logical zero.

To set the factor Ka, the binary code of the value N2 is set at the input inputs of the binary multiplier 6, associated with the coefficient K2 and the binary multiplier 6 ratio 6

N2 2M / K. ,

(four)

So, for example, if K2 is 4.12, and the binary multiplier is 6 devi-rand (M-9),

then, in accordance with (4), the value of N2 is approximately equal to 124 (binary code 001111100). Therefore, in this case, the switches of the third, fourth, fifth, sixth and seventh bits of the binary multiplier 6 must be connected to the logical zero bus.

Analog-to-digital converter 4 is built according to an analog-to-digital converter of the following type and contains (Fig. 2) a pulse generator 17 having two outputs, a comparison element 18 (comparator), a reversible counter 19 pulses, a digital-to-analog converter 20, and

5 three olement And 21-23. In this case, the first input of the comparison element 18 forms the input of the analog-digital converter 1. The outputs of the comparison element 18 are connected to the first inputs of the And elements 21 and 22. The outputs

The last 0 form the first and second outputs of the analog-digital converter 1, respectively, and are connected respectively to the input input and the subtraction input of the reversible counter 19. The information output of the reversible counter 19 (discharge outputs) is connected to the information input of the digital-analog converter 20 and forms the third output of the analog-digital converter 1. Output digital analog

0, converter 20 is connected to the second input of reference element 18. The first output of the pulse generator 17 forms the fourth output of the analog-digital converter 1. The second output of the generator 5 of the 17 pulses is connected to the second inputs

elements and 21 and 22 and forms the fifth

analog-to-digital converter output

1. The output element And 21 is also connected to

the first input of the decoder 23 zero, others

The 0 inputs of which are connected to the zero outputs of the bits of the reversible counter 19. The output of the decoder 23 forms the sixth output of the analog-digital converter 23.

5 All units of the device can be implemented on the domestic integral elements of a moderate degree of integration. So counters 2, 3, 4 and 19 can be assembled on K155IE7 microcircuits, counters 7 and 8 - on

0 chip K155IE6. binary multipliers 5 and 6 - on the K155IE8 chips.

The 10,11 and 23 zero decoders are a AND multi-input element, whose inputs are connected to zero

5 outputs of the relevant counters. Decoders 10, 11 and 23 can be assembled, for example, on chips 155LA2, trigger 12 - on a K155TM2 chip, and logic elements 12-15 and 21. 22 - on K155LAZ chips. A group of indicator lamps can be used as a digital display unit 16 type IV22. The pulse generator 17 can be assembled on K155LN1 microcircuits. K155TM2 and K155LAZ. Comparison element 18 can be built on a K140UD13 chip, and a digital-to-analog converter can be built on a K572PA1 chip.

The proposed analyzer for the content of silicon in molten iron works as follows.

The input of the analog-digital converter 1 receives a signal from the temperature sensor of the cooling sample of liquid iron. Converter 1 converts this signal into a parallel and reversible number-pulse code.

The principle of operation of the analog-digital converter shown in FIG. 2 is as follows. The analog signal X (t) corresponding to the current temperature T (t) at time t is fed to the first input of the comparison element 18. The second input of the comparison element 18 receives the compensating analog signal Y (t) of the feedback from the output of the digital-analog converter 20. If the signal X (t) is greater than the signal Y (t) (the Undercompensation mode), then the first output of the element 18 comparison, a logical unit signal is formed, which opens the element AND 21. At the same time, the pulses from the second output of the generator 17 through the open element 21 are fed to the addition input of the reversible counter 19 and the first output of the analog-to-digital converter 1. The content of the counter 19 is increased, which causes Increasing the compensating analog signal Y (t) at the output of the analog-digital converter 20. As soon as the signal Y (t) becomes equal to the signal X (t) up to the deadband of the comparison element 18, the middle element closes the 21 element.

If the signal X (t) being processed is less than the compensating signal Y (t) (Overcompressing mode), then the second output of the comparison element 18 forms a signal of the logical unit that opens the AND 22 element. At the same time, the pulses from the second output of the generator 17 are transmitted through the open element 22 to the subtraction input of the reversible counter 19 and the second output of the analog-to-digital converter 1. The contents of the counter 19 are reduced, which causes a decrease in the compensating signal Y (t). as soon as the signal Y (t) becomes equal to the signal X (t) with an accuracy of the deadband of the comparison element 18, the element 22 closes.

This ensures a consistent conversion of the signal being processed.

X (t) in digital form, in the course of which the first and second outputs of analog-digital converter 1 form a reversible number-pulse code — code pulses corresponding to elementary positive and negative increments of the signal being processed, and on the outputs of the bits of the reversible counter 19 is formed parallel binary code of the processed signal, which is fed to the third output of the analog-to-digital converter 1.

In addition, the fourth and fifth outputs of the analog-digital converter 1

5, two series of time-shifted clock pulses Gi and Ga from the generator outputs 17 are continuously received.

Before the next analysis cycle begins, a minimum signal from the sensor enters the input of the device and in the reversible counter 19 a number of zero is generated, which is selected by the decoder 23. At the time to start the measurement (Fig. 3), the signal at the output of the sensor begins to increase to

5, corresponding to the initial temperature of the melt, code pulses corresponding to a positive signal increment begin to form at the output of the element 21 (fig. 2). When appearing

0 of the first such pulse at the output of the decoder 23 (the sixth output of the analog-digital converter) appears the trigger signal 12. The trigger 12 is set to the zero state and the signal from the unit

5 outputs block element 14.

At the same time, the initial setup signal is fed to the control inputs of the result counter 7 and the second buffer counter 8. In this case, the code 7 is entered into counter 7

0, the value of Ko, and in the counter 8, the code of the value P, As a result, the output of the decoder 11 produces a control signal that turns off the digital display unit 16.

In the process of processing analog

5 signals, code pulses from the first and second outputs of the analog-digital converter 1 (outputs of elements 21 and 22, Fig. 2) arrive respectively at the inputs of the addition and subtraction of the threshold counter 2. As soon as a positive or negative signal increment exceeds the threshold, corresponding to the overflow output of the counter 2, pulses are generated, which are fed to the inputs of the initial installation of the counter 4 times. The clock inputs of the GI series from the fourth output of the analog-digital converter (the first output of the generator 17, Fig. 2) continuously go to the clock input of the counter 4 times.

In the time interval between the times to and c (Fig. 3), due to the high rate of change of the processed signal, the time counter 4 will be constantly reset to the initial state by overflow pulses of the threshold counter 2. Therefore, during the specified time interval, the time counter 4 does not have time to overflow.

At time ti (Fig. 3), the melt temperature reaches the equilibrium solidus temperature Ts. At the same time, as a result of the release of latent heat of crystallization, the melt temperature stabilizes for some time, which leads to the appearance on the graph T (t) of a specific site. Since changes in the processed signal do not exceed the threshold ± e0 at the appearance of the solidus pad, no pulses are generated at the output of the threshold counter 2, which means that the counter 4 times is reset to the initial state. As a result, at the moment of time 12 11+ T0 at the output of the overflow of counter 4 of time, a pulse is generated that sets trigger 12 to one state and simultaneously arrives at the control input of buffer counter 3.

When a signal is received at the control input of the buffer counter 3, the parallel binary code of the solidus temperature Ts is inserted into the last one from the third output of the analog-digital converter 1 (from the outputs of the bits of the reversible counter 19, Fig. 2). The occurrence of information in the buffer counter 3 triggers the decoder 10. Which opens the element And 13, As a result, the Ga series pulses from the fifth output of the analog-digital converter 1 (from the second output of the generator 17, Fig. 2) through the open element And 13 arrive to the input of the subtraction of the buffer counter 3 and through the binary multiplier 5 and the element OR 15 to the input of the subtraction of the counter 7 of the result.

In addition, after installation of the trigger 12, the element I 14 is opened to the unit state. In this case, the Gi series pulses from the fourth output of the analog-digital converter 1 (the first generator output 17, Fig. 2) are shifted in time relative to the Ga series pulses, through open element 14 and binary multiplier 6 are fed to the input of the subtraction of the buffer counter 8 and through the element OR 15 - to the input of the subtraction of the counter 7 of the result.

As soon as the number zero is formed in the buffer count 3, the decoder 10 blocks element 13 and, as a result, the flow of G2 series pulses to the subtraction inputs of counters 3 and 7 stops. Similarly, as soon as the number zero is formed in buffer counter 8, the decoder 11 blocks the element And 14, as a result of which the flow of pulses of the Gi series to the subtraction inputs of the buffer counter 8 and the counter 7 of the result is stopped,

Since the number of pulses of the G2 series received at the input of the subtraction of the buffer counter 3, and the number of pulses received

0 to the subtraction input of the result counter 7, is related to the proportionality coefficient Ki, given by the binary multiplier 5, then when the contents of the buffer counter C change from Ts to zero, the content of the result counter 7 changes to KiTj.

Similarly, since the number of pulses of a series Gi arriving at the input of the subtraction of the buffer counter 8 and the number of pulses

If the 0 arrivals to the subtraction input of the counter 7 result are related by the proportionality coefficient K2, given by the binary multiplier 6, then when the contents of the buffer counter 8 change from the value P to

5 zero, the contents of counter 7 of the result is changed by the value of K2P.

Consequently, by the time when the contents of the buffer counters 10 and 11 become zero, the contents

0 of the result counter 7 is changed from the value of K to the value of Si K o - KiTs K2P, wherein the signal from the output of the decoder 11 simultaneously with the blocking of the element I 14 switches on the digital block 16

5 indications. The indicator lamps of the latter display the result of analyzing the percentage of silicon in the melt sample.

Thus, the proposed analyzer, in contrast to the known ones, makes it possible to determine the silicon content in both hypoeutectic and hypereutectic cast iron, and does not imply a mandatory appearance on the cooling curve of the temperature of the liquidus platform. At the same time, the scheme of the proposed device allows you to automatically enter the required correction for the phosphorus content, which improves the accuracy of determining the silicon content in the cast iron sample and expands the field of application of the device.

The use of the device in the foundry and blast furnace production allows an average decrease of 20% by an average of 20%.

5 deviations in silicon, which provides savings in consumption of ferrosilicon for metal finishing.

Claims (1)

The claims of the analyzer of the content of silicon in liquid iron, containing analog-digital a converter whose input is a device input, a threshold counter, the addition and readout inputs of which are connected respectively to the first and second outputs of the analog-digital converter, the first buffer counter, whose information input is connected to the third output of the analog-digital converter, a time counter, whose counting input is connected to the fourth output of the analog-to-digital converter, and the inputs of the initial installation of the time counter are connected to the overflow outputs of the threshold counter, the first element The Ient, the first input of which is connected to the fifth output of the analogue of the digital converter, the first binary multiplier and the first decoder zero, whose information input is connected to the bit outputs of the first buffer counter, and the output connected to the second input of the first I element, the output of which is connected to the subtracting input of the first buffer counter and the input of the first binary multiplier, the second binary multiplier, the result counter and the digital indication unit, the output of which is the output of the device, the information input of the block of digits howl indication associated with the result outputs bit rows counter, a trigger, an OR gate and a second AND gate having a first input koto- connected to the trigger output, and the time counter overflow output is connected to the first trigger input and control input of the first buffer counter, so that, in order to improve the accuracy of the analysis and expand the analyzer’s use area , a master zeroer, a second zero decoder, and a second buffer counter, the subtraction input of which is connected to the output of the second binary multiplier, are entered, the information output of the master is connected to the information input of the second buffer counter, the output of the first binary multiplier, and the output of the OR element is connected to the subtraction input of the result counter, the information input of the second decoder zero is connected to the outputs of the bits of the second buffer counter, and the output of the decoder zero is connected to the control input of the digital display unit and the second input of the second element And, the third input of which is connected to the fourth output of the analog-digital converter, and the output is connected with the second OR element and the input of the second binary multiplier, the sixth output of the analog-digital conversion L conn li ne to the control inputs of the result counter and a second counter buffer, and to the second input flip-flop. IE FIG 3 21  (2) - CZ) (7.8.12)