SU1739493A2 - Apparatus for separating first and latest pulses in train - Google Patents

Abstract

The invention: the device contains a delay element 1, D-triggers 2, 3, elements OR 4, 5, 26, elements AND-NOT 6, 7, elements 14, 15 comparison, registers 12, 13, generator 16 clock pulses, inverters 17 , 18, pulse formers 19, 20, And 21, 22, 23, 24, 25 elements, decoder 27, RS-triggers 28,29,30, pulse counter 31, code buses 32, 33, input bus 8, reset bus 9 , output tires 34, 35, control bus 36. 1 Il.

Description

UNION OF SOVIET

SOCIALIST

REPUBLIC

<n> SU <. „1739493 A2 <51) 5 Н 03 К 5/153 ________________________

STATE COMMITTEE ON INVENTIONS AND DISCLOSURES UNDER SCSTAN OF THE USSR

DESCRIPTION OF THE INVENTION

TO COPYRIGHT CERTIFICATE (61) 1403353 (21) 4804983/21 (22) 03/23/90 (46) 07/06/92. Bull. No. 21 (71) Moscow Institute of Civil Aviation Engineers (72) S.Zh. Kishensky, S.V. Kamensky, V.B. Panova and O.Yu. Khristenko (53) 621.374 (088.8) (56) USSR Copyright Certificate No. 1403353, cells, H 03 K 5/153, 1988.

(54) DEVICE FOR ISSUING THE FIRST AND LAST PULSE IN THE SERIES (57) Summary of the invention: the device contains a delay element 1, D-triggers 2, 3, OR elements 4, 5, 26, AND-NOT elements 6, 7, elements 14, 15 comparisons, registers 12, 13, clock generator 16, inverters 17, 18, shapers 19, 20 pulses, elements 21, 22, 23, 24, 25, decoder 27, RS-triggers 28,29,30, counter 31 pulses, code buses 32, 33, input bus 8, reset bus 9, output buses 34, 35, control bus 36. 1 ill.

1739493 A2

The invention can be used in devices for processing pulsed signals from control systems, telecontrol and telemetry and is an improvement of the device according to the main auth. No. 1403353.

A device is known for separating the first and last pulses in a series, containing two output buses, two D-. a trigger, the D-input of the first of which is connected to a common bus, and a delay element, the input of which is connected to the input bus of the device.

A disadvantage of the known device is the strict restriction on the period of the succession of pulses in the series and narrow functionality.

Closest to the proposed device is a device containing two output buses, two D-flip-flops, a delay element, a reset bus, an input bus, two AND-NOT elements, and two OR elements, the D-input of the first D-trigger connected to a common bus, the input of the delay element is connected to the input bus, the output of the first OR element is connected to the first output bus, the first input to the first input of the second OR element, with the direct output of the second D-trigger and the first input of the first AND-NOT element, and the third input to the output delay element, C-input of the first D trigger and W the first input of the second OR element, the output of which is connected to the second output bus, and the third input - with the direct output of the first D-trigger, the R-input of which is connected to the input bus and with the first input of the second element AND NOT, and the output with C- the input of the second D-flip-flop, the D-input of which is connected to its inverse output, and the R-input is connected to the reset bus.

The disadvantage of the main invention is the lack of control over the duration and period of the pulses in series, which reduces the functionality. Emerging interference pulses can cause the merging of adjacent series of pulses (useful) or suppress extreme pulses of the series, which causes incorrect operation of the device.

The purpose of the invention is the expansion of the functionality of the device by forming control pulses. At a value of durations and periods of pulses less than the maximum permissible values.

This goal is achieved by the fact that two storage registers, two comparison elements, a clock pulse generator, two inverters, two pulse shapers, five AND elements, a third OR element, a decoder, three RS-flip-flops are introduced into the device for separating the first and last pulses in the series , a pulse counter, two code buses, two control buses, two output buses, the first and second code buses being connected respectively to the information inputs of the first and second storage registers, the sync inputs of which are connected respectively enno the first and second control buses, the outputs - the first groups, respectively, with inputs of the first and second comparison elements, the second group of inputs of which. connected to the outputs of the pulse counter and the inputs of the decoder, the output of which is connected to the R-input of the first RS trigger, the inverse output of which is connected to the first input of the first AND element and to the first input of the third OR element, the output of which is connected to the R-input of the pulse counter, the second input is with the output of the first pulse shaper, with the first input of the second element And, with the second input of the first element And and with the S-input of the first RS-trigger, the direct output of which is connected to the second input of the second and the first input of the third elements And, the second input d of the third element And is connected through the second pulse former to the input bus, which is connected through the first inverter to the input of the first pulse former, the third inputs of the second and third elements And are connected respectively to the outputs of the first and second comparison elements, the outputs, respectively, to the S-inputs of the second and third flip-flops, the R-inputs of which are connected to the output of the first AND element, the outputs corresponding to the first inputs of the fourth and fifth And elements, the second inputs of which are connected through the second inverter with the output to orogo OR gate, the outputs respectively from the third and fourth output lines, the clock pulse generator is connected to the pulse counter Svhodom.

The drawing shows a structural diagram of a device for highlighting the first and last pulses in a series.

The device contains a delay element 1, the first and second D-flip-flops 2 and 3, the first and second elements OR 4 and 5, the first and second elements I-N E 6 and 7, the input bus 8, the reset bus 9, the first and second output buses 10 and 11, the first and second storage registers 12 and 13, the first and second comparison elements 14 and 15, the clock pulse generator 16, the second and first elements HE 17 and 18, the first and second pulse shapers 19 and 20, the second 21, the third 22 and the first 23 elements And, the fourth and fifth elements And 24 and 25, the third element OR 26, the decoder 27, the first, second and third RS-triggers 28-30, count pulse 31, first and second code buses 32 and 33, third and fourth output buses 34 and 35, control buses 36. The output of element 1 is connected to the C-input of trigger 2 and to the first inputs of elements 4 and 5. The direct output of trigger 2 is connected with the second input of element 5, inverse with the second inputs of elements 4 and 6. The direct output of trigger 3 is connected to the second input of the element bis by the third inputs of elements 4. and 5, the inverse output is with the D-input of trigger 3. The outputs of elements 4 and 5 are connected with tires 10 and 11, respectively, the output of element 5 through element 17 is connected to the second inputs and elements 24 and 25. The output of element 6 is connected to the first input of element 7, the output of which is connected to the C-input of trigger 3. Bus 8 is connected to the second input of element 7 and to the inputs of elements 1, 18, 20, and to the S-input of the trigger 2. The bus 9 is connected to the R-input of the trigger 3. The outputs of the registers 12 and 13 are connected to the first inputs of the elements 14 and 15, respectively, the outputs of which are connected respectively to the first inputs of the elements 21 and 22. The output of the generator 16 is connected to the C-input of the counter 31. The output of the element 18 through the former 19 is connected to the second input of the element 21 and to the first inputs and elements 23 and 26, with the S-input of the trigger 28. The output of the driver 20 is connected to the second input of the element 22. The outputs of the elements 21 and 22 are connected to the S-inputs of the triggers 29 and 30, respectively, the R-inputs of which are connected to the output of the element 23. The outputs elements 24 and 25 are connected respectively to the third and fourth output buses 34 and 35 of the device. The output of the element 26 is connected to the reset input of the counter 31. The output of the decoder 27 is connected to the R-input of the trigger 28, the direct output of which is connected to the third inputs of the elements 21 and 22, and the inverse output is connected to the second inputs of the elements 23 and 26. The outputs of the triggers 29 and 30 are connected with the second inputs of the elements 24 and 25, respectively. The output of the counter 31 is connected to the second inputs of the elements 14 and 15 and to the input of the decoder 27. The input buses 32 and 33 are connected respectively to the information inputs of the registers 12 and 13, to the C-inputs of which the corresponding control buses 36 are connected.

The device operates as follows.

The operation of blocks 1-7 is identical to the operation of similar blocks of the main invention. The pulse of negative polarity on the reset bus 9 trigger 3 is set to the initial zero state.

A bus 8 receives a series of pulses of negative polarity at the input of the device. On the first pulse of the series, trigger 2 is set to a single state. 5 At the same time, the high potential from the direct output of trigger 2 closes the OR element 5, and the low potential from the inverse output opens the OR element 4. The first input pulse of the series, inverting by element 7, 10, sets trigger 3 to a single state, while the high potential from the direct output trigger .3 closes elements 4 and 5. The second pulse of the series confirms the single state of trigger 2 15 and the output of element 7 sets trigger 3 to zero, opening elements 4 and 5. The first input pulse of the series, delayed by element 1, is received at the C-input latch elements 2 and inputs OR 4 and 5.

In this case, the OR 4 element will be open at three inputs and at its output. A negative pulse is formed, the duration of which is equal to the duration of the first delayed pulse of the series. OR element 5 at 25 is closed by the high potential of the inverse output of trigger 2. At the end of the pulse from the output of element 1, trigger 2 is set to zero, opening element OR 5 and closing element 30 OR 4. The third output pulse of the series sets triggers 2 and 3 to unity state, closing the elements OR 4 and 5. At the end of the second delayed pulse from the output of element 1, trigger 2 is set35. is in the zero state. At the same time, there is a high potential at the inputs of the AND-NOT 6 element, a low potential appears at its output, which translates trigger 3 to the zero state through the AND-NOT 7 element, closing the 40 AND-NOT 6 element.

Further, for each input pulse of the series, triggers 2 and 3 are set to a single state, and then, at the end of the previous pulse delayed by it45 from the output of element 1, they are returned to their original state. Thus, after the last delayed pulse of the series on element 1, triggers 2 and 3 will be in the zero state, opening the element OR 50 5 and closing the element OR 4. Therefore, when forming on element 1 the last pulse of the series, at the output of element 5 (on the bus 11) a negative impulse is formed, the duration of which 55 is equal to the duration of the last pulse of the series.

Thus, this part of the device gives out pulses to the output buses that correspond in duration to the first and last pulses of the series and with a delay

Ί them for the same amount. After that, the device is automatically reset.

If a single pulse (which is considered an obstacle) is received at the input of the device, then triggers 2 and 3, when set to a single state, close the OR elements 4 and 5. At the end of the pulse from the output of Delay Element 1, trigger 2 is set to zero, at the inputs of element 6 - high potentials, which leads to the translation of trigger 3 in the zero (initial) state. Thus, from single pulses at the outputs 10 and 11 of the device, pulses are not formed, and the device is set to its original state.

The remaining units of the device generate control information, indicating that there is at least one pulse in the pulse train, the repetition period of which or its duration is below the permissible value, which gives the user a basis for deciding on the presence of interference from a series of information pulses .

In the initial state, the values of the minimum allowable duration and the minimum allowable period of the series pulses are entered in registers 13 and 12, respectively. The values are entered by setting the codes corresponding to the specified minimum values (their binary equivalents, and the pulse period from the generator 16) as an elementary unit of time at the information inputs of the registers (on buses 32 and 33). This allows you to quickly change the tolerance parameters and use a computer to analyze the parameters of a series of pulses. The installation is carried out by applying clock pulses to the clock inputs of the respective registers 12 and 13 via the control buses 36.

In the initial state, the triggers 28 and 30 are in the zero state, and with the positive potential from the inverse output through the OR element 26, the trigger 28 keeps the counter 31 in the zero state.

When the first pulse of the analyzed series arrives at its inverted negative edge, shaper 19 is triggered, a short positive pulse from its output goes to the input of element And 21, which, however, is closed at this point in time by low potentials from trigger 28 (like element And 22). The pulse from the output of the shaper 19 is also fed to the input of the element And 23 and sets the triggers 29 and 30 to the zero state (or confirms ngo) using a high-resolution high potential from the trigger 28. The same pulse generates a reset signal to the counter 31 and sets the trigger 28 to a single state. This pulse must be short enough to end before the trigger 28, switching to a single state, opens the And 21 element.

After setting the trigger 28 to a single state, the counter 31 starts the counting of pulses from the generator 16. In elements 14 and 15, the contents of the counter 31 are compared with binary numbers corresponding to the minimum value of the pulse duration and repetition period in a series. The output signal of the comparison elements takes a single value when the contents of the counter are less than the second compared number.

At the end of the first pulse of the series (this moment characterizes the duration of the first pulse of the series), the positive trailing edge of the pulse causes the appearance of a short pulse at the output of the driver 20, which arrives at element 22. If at this point the contents of the counter 31 are less than the value recorded in register 13, s the output element 15 is supplied to the element 22 positive potential. Thus, when the pulse duration is less than the threshold value (permissible), a positive pulse is generated at the output of the And 22 element, which sets the trigger 30 to a single state.

The beginning of the next pulse of the series is accompanied by the appearance of a short positive pulse from the output of the shaper 19. Similarly, this pulse is fed to the input of the element And 21, at the other input of which the potential from the output of the comparison element 14 has a positive value if, by the time the pulse of the series ends, the contents of the counter 31 are less than the value the number recorded in the register 14. In this case, the element 21 is triggered and the trigger 29 is set to a single state, fixing the output of the period of the next pulse of the series beyond the tolerance.

The pulse from the output of the shaper 19 confirms the single state of the trigger 28 and resets the counter 31 through the OR element 26, after which the analysis of the duration and period of the next pulse begins.

If the duration and period of the pulse are within the tolerance, signals from the outputs of the comparison elements 14 and 15 are not formed.

The fact of the end of the current series of pulses is fixed by the decoder 27, which generates a positive signal at the moment of time corresponding to the state of the counter N _C m = τ ₃ / T _g , where t ₃ and T _g are the delay time of element 1 and the pulse repetition period from the generator 16 At the same time, the device makes a decision to end the next series of pulses. It is at this moment that the last impulse of the series from the output of the OR 4 element is formed.

By the signal from the decoder 27, the trigger 28 is set to zero, stopping the counter of the counter 31 and giving an enable signal to the I 23 elements. The last pulse of the series, converting to positive on the HE 17 element, goes to the second inputs of the I 24 and 25 elements 15 at the outputs of which, during the duration of the last pulse of the series, positive signals are generated in the following cases: at output 35, if there is at least one pulse in the series of pulses, the duration of which is less than the permissible length; output 34 — if there is at least one pulse in the series whose period is less than the permissible one.

The units of the device are in the state described 25 until the start of the next series of pulses, with the arrival of the first pulse of which the trigger 28 is set to a single state, and the triggers 29 and 30 to zero. Further, the operation of the device is similar. thirty

Thus, the proposed device, in addition to the functions provided by the main invention, provides the formation of signal pulses, indicating the correspondence of the time parameters of pulses in series with an acceptable value. Thus, the noise immunity of the device is also increased, since it is possible to exclude from the consideration a series of pulses in 40 of which sections affected by interference were detected.

The delay value of element 1 is selected from the relation Tmax <t ₃ <2 - Tmin, where T _M in and Tmax ~ respectively minimum 45 and maximum pulse repetition periods in a series.

Upon receipt of a single pulse at the input of the device, a decision on its duration is also made, however, since 50 this pulse does not appear on bus 11, the control signals are not read out from buses 34 and 35; upon the arrival of the next series of pulses with the first pulse, the device is set to its initial state 55, so single pulses do not affect the operation of the device,

Claims (1)

Claim A device for highlighting the first and last pulses in a series by ed. No. 1403353, characterized in that, in order to expand the functionality by forming control pulses with pulse durations and periods shorter than the maximum permissible values, two storage resistors, two comparison elements, a clock generator, two inverters, two are introduced into it pulse shaper, five AND elements, third OR element, decoder, three RS triggers, pulse counter, two code buses, two control buses, two output buses, the first and second code buses being connected respectively only with the information inputs of the first and second storage registers, the sync inputs of which are connected respectively to the first and second control buses, the outputs are respectively with the first groups of inputs of the first and second comparison elements, the second groups of inputs of which are connected with the outputs of the pulse counter and with the inputs of the decoder, the output of which connected to the R-input of the first RS trigger, the inverse output of which is connected to the first input of the first AND element and to the first input of the third OR element, the output of which is connected to the R-input of the pulse generator, the second input is with the output of the first driver, with the first input of the second element And, with the second input of the first element And and with the S-input of the first RS trigger, the direct output of which is connected to the second input of the second and the first input of the third elements And, the second input the third element And is connected through the second pulse shaper to the input bus, which is connected through the first inverter to the input of the first shaper, the third inputs of the second and third elements And are connected respectively to the outputs of the first and second elements inputs, outputs, respectively, with the inputs of the second and third triggers, the R-inputs of which are connected to the output of the first AND element, the outputs, respectively, with the first inputs of the second and third AND elements, the second inputs of which are connected through the second inverter with the output of the second OR element, the outputs, respectively with the third and fourth output buses, and the clock is connected to the C-input of the pulse counter.