SU1730713A1 - Digital frequency discriminator - Google Patents

Abstract

The invention relates to the field of radio engineering and can be used to demodulate frequency-modulated and frequency-manipulated signals in radio receivers and radio measuring devices. The purpose of the invention is to increase the reliability of the telegraph signal by eliminating the ambiguity of its allocation. Digital frequency detector contains pulse generator 1, control pulse generator 2, reference generator 3, first 4 and second 11 triggers, first 5, second 6, third 12 and fourth 14 elements AND, first 13 and second 15 elements OR, first 7 and the second 16 pulse counters, the first 8 and the second 10 memory blocks and the comparison unit 9. The digital frequency detector makes it possible to eliminate the fragmentation (failures) of the telegraph signal at the detector output, due to asynchronous input frequency and frequency of the reference oscillator, 1 Il.

Description

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The invention relates to the field of radio engineering and can be used to demodulate frequency-modulated and frequency-manipulated signals in radio receivers and radio measuring devices.

The purpose of the invention is to increase the reliability of the telegraph signal by eliminating the ambiguity of its allocation.

The drawing shows the functional electrical circuit of the proposed digital frequency detector.

The proposed digital frequency detector includes a pulse shaper 1, a control pulse shaper 2, a reference oscillator 3, a first trigger 4, a first 5 and a second 6 And elements, a first pulse counter 7, a first memory block 8, a comparison block 9, a second memory block 10 TI, the second trigger 11, the third element And 12, the first element OR 13, the fourth element And 14, the second element OR 15 and the second pulse counter 16.

Digital frequency detector works as follows.

The high-frequency frequency-manipulated signal is fed to the input of the pulse driver 1. This is the zero-crossing driver, at the output of which short signals are generated. From the output of the reference generator 3 to the input of the generator of control pulses 2 and to the inputs of the elements 12 and 14, clock pulses are given, the frequency of which is higher than the frequency of the input signal. The control pulse generator 2 controls the operation of pulse counters 7 and 16 and, through elements 5 and 6, the operation of memory blocks 8 and 10. The first clock pulses following the signal pulses are extracted in the control pulse former 2 and arrive at logical elements 5 and 6. Depending on the state of the first trigger 4, the code is copied from the first pulse counter 7 to the first memory block 8 or from the second pulse counter 16 to the second memory block 10. Also, depending on the state of the first trigger 4, the clock pulses from the reference generator 3 arrive through the logic elements AND 12 and OR 13 to the counting input of the first counter 7 pulses or through the logic elements AND 14 and OR 15 to the counting input of the second counter 16 pulses. In blocks 8 and 10 of the memory, the numerical values of the periods, expressed in binary code, are recorded. The second clock pulses produced in the driver 2 for the control pulses are fed to the setting inputs of the pulse counters 7 and 16 and

set them to zero. In the control pulse shaper 2, a third control pulse is also generated, which coincides in time with

first and second clock pulses. This pulse is applied to the blocking inputs of counters 7 and 16 pulses, stopping their start by the first two clock pulses of the reference generator 3. As a result, depending on the state of the first trigger 4, either the first pulse counter 7 or the second pulse counter 16 are filled with clock pulses the period of the input signal. Those.

5, the counters 7 and 16 pulses are filled with the clock pulses alternately. The first pulse counter 7 is filled until the next signal pulse appears, after which the next clock pulse

0 through the first element AND 5 will make a code override from the pulse counter 7 into the memory block 8. With the appearance of the next signal pulse, the second pulse counter 16 is filled with clock pulses,

5 Another clock pulse through the second element And 6 will produce a code override from the second pulse counter 16 to the second memory block 10. Thus, in memory blocks 8 and 10, a census of code occurs

0 alternating with a period twice as large as the period of the input signal pulses shifted in time by the period of the input signal pulses. It follows that codes in blocks 8 and 10 of memory will be recorded.

5 are the same if there was no change in the frequency (period) of the input signal. When changing the frequency (period) of the input signal, if the previous period was different in duration from the subsequent period, then this

0 will result in writing different codes in memory blocks 8 and 10. If the code in memory block 8 is larger than the code recorded in memory block 10, then from block 9 comparison (output) through the element OR 13 to the first counter 5 pulses 7 will be added to the unit of the lower-order bit. If the code in memory block 10 is larger than the code in memory block 8, then from unit 9 of comparison (output) through the element OR 15, a second low-order unit will be added to the second counter 16 for 0 pulses. A code change in the counters 7 and 16 pulses immediately changes the code in blocks 8 and 10 of the memory. It follows that with different codes in blocks 8 and 10 of memory,

5, the communication unit 9 of the comparison through the elements OR 13 and 15, the smaller code is increased by one least significant bit. Therefore, with a constant frequency, the resulting difference in codes in the memory blocks will be corrected, which will lead to no fragmentation (malfunction) of the output signal at the output of the digital frequency detector. At the output of comparison unit 9 (output), if the input codes from memory blocks 8 and 10 are equal, a voltage equal to 1 occurs. If the input codes from memory blocks 8 and 10 are not equal, the output of comparison unit 9 produces voltage O. As soon as the change in the frequency (period) of the input signal stops, a signal with level 1 is set again at the output of the comparison block 9, the telegraph signal is released from the output of the second flip-flop 11 when operating in the MPPT mode. At the other output (input of the second trigger 11), a pulse is emitted, the duration of which is equal to the duration of the transient from one frequency of the input signal to another value of the frequency of the input signal to another value of the frequency of the input signal,

The proposed digital frequency detector makes it possible to eliminate the splitting (failures) of the telegraph signal at the detector output, due to the synchronism of the input frequency and the frequency of the reference oscillator, which is very important when using such a detector in instrumentation equipment.

Forming 1 pulses can be performed on integrated circuits of the type 140UD7. Comparison unit 9 may be performed on an integrated chip of the 533SP1 type. Shaper 2 control pulses, pulse counters, triggers, AND and OR elements can be performed on a series 133 integrated circuits.

Claims (1)

Invention Formula A digital frequency detector containing a serially connected pulse generator, the input of which is an input of a digital frequency detector, and a driver of control pulses, the clock input of which is connected to the reference generator, the first trigger, the counting input of which is connected to the output pulse former, and direct and inverse outputs — with the first inputs of the first and second elements, respectively, the second inputs of which are combined and connected to the write pulse output — a pilot pulse former that is connected in series to the first pulse counter and the first memory block, whose outputs connected to the first group of inputs of the comparison unit, as well as the second memory block, the outputs of which are connected to the second group of inputs of the comparison unit, and the second trigger, the counting input of which is connected to the output Equals the block with The output is the output of the digital frequency detector, wherein the outputs of the first and second elements I are connected to the recording inputs of the first and second memory blocks, respectively, and the setup input and the blocking input of the first pulse counter are connected to the corresponding outputs of the control pulse generator, which differs By the fact that, in order to increase the reliability of the telegraph signal by eliminating the ambiguity of its separation, the third And elements and the first OR element are introduced, the output is connected to the counting input of the first pulse counter, and the fourth element AND, the second element OR and the second pulse counter, the outputs of which are connected to the information inputs of the second memory block, and the first inputs of the third and fourth elements AND are connected to the output generator, the second inputs of the third and fourth elements And are connected respectively to the direct and inverse outputs of the first trigger, the installation input and the lock input of the second pulse counter connect with the corresponding inputs of the first pulse counter, and the second inputs of the first and second OR elements are connected to the Less and More Comparison Units, respectively.