SU1728976A2 - Data communication system - Google Patents

Abstract

The invention relates to telecommunications and may find application in data transmission systems. The aim of the invention is to improve the noise immunity. The data transmission system contains on the transmitter side an input and a matching unit, an encoder, a digital transmitting filter, permanent storage units, a signal converter, a digital-analog converter, a low-pass filter and an output matching unit, and side - clock generator, controllable divider, control unit, memory blocks, program counter, subtractors, switches, adders, multiplier, fast Fourier transform unit, in terminating discharge unit, an analog-digital converter, the adaptive equalizer, deciding unit, a decoder, an output matching unit and a control unit. In this system, in the adaptive equalizer for each cycle of transformation consisting of n points. Each weighting factor is formed only once and the number of adaptations for obtaining output data is reduced by n times. Consequently, the value of the constant coefficient in the recursive algorithm of the adaptive equalizer can be increased in time, thereby increasing the noise immunity. 2 Il. (Ls

Description

The invention relates to telecommunications, can be used in data transmission systems and is an improvement of the invention according to the authors. St. No. 1462507.

The aim of the invention is to improve the noise immunity.

FIG. 1 and 2 show the structural and electrical diagrams of the transmitting and receiving sides of the system, respectively.

The data transmission system comprises on the transmitting side an input matching unit 1, an encoder 2, a digital transmitting filter 3, a first permanent storage unit 4, a signal converter 5, a digital-to-analog converter 6,

a low-pass filter 7, an output matching block 8 and a second permanent storage unit 9, wherein the digital transmitting filter 3 comprises a multiplier 10, a block 11 of the inverse fast Fourier transform and a block 12 fast Fourier transform, and on the receiving side a clock frequency generator 1, control divider 2, control block 3, first 4 and second 5 memory blocks, program counter 6, first subtractor 7, third memory block 8, first switch 9, first adder 10 (multiplier 11, second subtractor 12, fourth block 13 memories, second ummator 14, block 15 bystch

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Fourier transform, input matching unit 16, analog-to-digital converter 17 and adaptive equalizer 18, containing fast Fourier transform unit 19, correction units 20, inverse fast Fourier transform unit 21, synchronous detector 22, multiplier 23, first permanent memory unit 24, memory blocks 25, counters 26, subtractors 27, reference signal unit 28, frequency response indicator 29, modulator 30, second storage unit 31, divider 32, display counter 33 and noise indicator 34, as well as decision block 35, decode 36, an output matching unit 37, a fifth unit 38 memory, the second switch 39 and the control unit 40.

The input matching unit 16 of the receiving side of the data transmission system serves to maintain a constant level of the input signal. In addition, the input matching unit 16 includes a Hilbert transducer. The analog-to-digital converter 17 consists of two parts, respectively, for the in-phase and quadrature components of the signal. The in-phase and quadrature components of the signal in the device are alternately processed. The sampling / receiver frequency is assumed to be equal to Rdr. Pr 2 FT. The signal from the output of the adaptive equalizer 18 is fed through the synchronous detector 22 and multiplier 23 to decision block 35, which evaluates the received information symbols an min Vxn - ai /, here min 1b (x) is the inverse function of minf (x), those. taking the value of the argument x minimizing b (x).

Adaptive corrector 18 serves to combat linear distortions. It operates in the frequency domain using Blocks 19 for 32 and 64 dots. Block 21 is also implemented. Between blocks 19 and 21, correction blocks 20i, ..., 20n are included, representing in the simplest case multipliers or adders. The signal from decision block 35 is supplied through modulator 30 to block 28 of the reference signal, which can be performed identically with blocks 19 (21).

The reference signal from the output of block 28 and delayed by the memory blocks 25i, ..., 25n of the signal from the outputs of the corrective

blocks 20–20p are compared in the subtractors 27i27P, and the error signal with the corresponding sign bit is supplied by means of counters 26i, ... 26n to adjust the correction blocks 20i, ... 20n. Before

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the beginning of the correction, the counters are set to the nominal position (in decimal terms).

Here can also be carried out

5 indication of frequency characteristics with the help of frequency response indicator 29; With the help of splitter 32 and indication counter 33, the rate of correction adjustment can vary depending on the value of the signal-to-noise ratio. When the task of displaying the characteristics and the signal-to-noise ratio is not set, the divider 32 and the indication counters 33 are not required. For a clock synchronization, 2 samples are taken from a single interval.

Using a 2-, 4- or 8-point block 15 for clock synchronization, the signals of the first samples are converted, then the second samples corresponding to the single samples.

20 intervals. The difference in the sum of certain frequencies from the output of block 15 of the first and second samples is fed through the second switch 39, program counter b, blocks 13 and 38 of memory to the control block 3, the sum of the signal of these frequencies from the output of block 15 is performed in the first adder 10. Signals of two spectrum frequencies can be summed up here.

In certain cases it is enough

30 signals of one frequency of the spectrum, i.e., without summation. Thus, the frequencies that most contain information about the clock frequency are used here. All this provides quick

35 connection without a configuration signal combination, which is very important in the case of interruptions in communication from various kinds of interference and during switching. In order to increase the synchronization accuracy, a correction can be introduced, which is determined by the influence of the distortion of the characteristics of the communication channel, into the second subtracter 12 after entering into the communication. a multiplier 11 for the sum from the second adder 14. The result is fed to the first subtractor 7 and the first memory block 4. Further, as described above. In most cases, it is not necessary to sum the first adder 10 during each cycle of block 15. Therefore, a second can be included between the second subtractor 12 and the second adder 14.

55 block 5 of memory. Depending on the requirements, a clock error may be isolated from the in-phase component of the signal, from the quadrature component of the signal, or from both components.

After the connection is made, the signal to the first adder 10 can be supplied from the outputs of the correction units 20, and from the output of the unit 15, the signal is not supplied.

First, the first sample is converted using block 19, the signals of which from the outputs of the correction blocks 20 are fed to the first adder 10. The second samples are then converted.

If you do not feed the carrier frequency to the input of block 21, to obtain an undistorted demodulated signal from the output of block 21, it is necessary to complicate the circuit of block 21. Therefore, in many cases, it is advisable to also feed the carrier frequency to the input of block 21. Then, the output of block 21 requires the synchronous detector 22, the second input of which is connected to the corresponding input of the block 21. The block 22 includes a carrier frequency clock with an error isolation circuit that has been traditionally performed.

In addition, in order to have a signal with a carrier frequency at the output of the reference signal unit 28, similarly to the signal at the outputs of the correction units 20, the modulator 30 is turned on before the reference signal unit 28.

Before launching the device from the second permanent storage unit 31, a corresponding signal is supplied to the unit of reference signals 28, which bring the corrector counters 26 into position for the best possible elimination of distortions in the communication channel, depending on the number of overpasses in it. This will additionally speed up communication, which is of great importance when the synchronization error is cleared by counter 26.

The second storage unit 31 may be installed after the block of reference signals 28, but in this case, the signals in the second storage unit 31 must be recorded in the frequency domain. Blocks 13 and 38 of memory, included at the output of software counter 6, make it possible to more accurately select the required moment of signal to control unit 3.

By turning on the output of the second adder 14, the third memory block 8 and the second subtractor 12, the output of which is connected to the input of the second switch 39, we can do without small blocks 11, 7, 4, 14, 15, 9 and this significantly reduce the number of computational operations. Then the error signal for the synchronization circuit is removed from the outputs of the counters 26. Moreover, this signal can be taken from one counter (for example, from the counter of the corresponding carrier frequency) or from several. or from all meters 26, depending on the requirement for accuracy and quality of the communication channel.

The signals after this Fourier transform cycle from counters 26 are summed in the second adder 14 and fed to the third memory block 8. And counter signals

0 26 after the next cycle, summing up in the second adder 14, are subtracted in the second subtractor 12 from the number recorded in the third memory block 8, and an error in one or another polarity goes to the second switch 5, etc. When there is no synchronization error at the outputs of counters 26, the signal is close to 0. When a synchronization error appears, the signal at the output of counters 26 deviates from 0 to one side or the other, and this

0 an error is detected at the output of the second subtractor (reference element) 12. Next, the error through the second switch 39, the programmable counter 6 and the corresponding blocks 13 and 38 of the memory is fed to

5 control unit 3.

In the simplest case, from the counter 26, it is sufficient to send a signal from the sign bit directly to the memory blocks 13 and 38, i.e. when the error deviates in one direction, a signal is sent to subtract the pulse in the controllable divider, and when the error deviates in the other direction, a signal is given to add a pulse.

When the correction blocks are multipliers, before the correction begins, the counters 26 are set to the B nominal position (in tenth unit), and in the correction process, an error signal with one sign or another will be introduced to the unit.

In the process of correction in the meters 26, in accordance with the distortions, the value will deviate from the nominal one or the other. With this number from counters

5 26 multiplies in the correction block 20 the numbers coming from the output of block 19, which minimizes the error.

The device can operate both by the absolute error criterion n and by the quadratic error criterion n2. In the first case, the error value in the correction unit 20 is directly multiplied by the correction signal supplied to its input. In the second case, in correction 5 we go to block 20, the preliminary values of the error are squared, and then multiplied by the signal supplied to the correction block 20, i.e. Correction is performed. The rms error criterion means that the error signal averaged by the counters 26 is squared in the corrective blocks 20.

Since in the adaptive equalizer 18 for each conversion cycle consisting of n points, each weighting factor is formed only once, the number of adaptations for obtaining output data is reduced by n times. Consequently, the value of the constant coefficient in the recursive algorithm of the adaptive corrector can be increased n times, respectively. This increases noise immunity and increases convergence speed.

Increasing the value of a constant coefficient for less frequent adaptation allows to reduce the required resolution of the weighting coefficients of the corrector in the frequency domain by n times. Therefore, the number of binary bits required to fill each weighting factor can be reduced loga n times, which simplifies the formation of weighting factors.

Claims (2)

1. The data transmission system on the bus. No. 1462507, characterized in that, in order to increase noise immunity, first and second switches, second, third, fourth and fifth memory blocks, a second subtractor and a control unit are inserted on the receiving side, while the output of the analog-digital converter is connected to the input of the fast Fourier transform unit through the first switch, the output of the first subtractor is connected to the first input of the program counter via the second switch, the output of the second adder is connected to the inputs of the second and third memory blocks, the outputs of which are Connected to the inputs of the second subtractor, the output of which is connected to the second input of the second switch, the second output of which is connected to the second input of the program counter, the output of which is connected to the second input of the controlled divider via the fourth memory block connected in series and the control unit, the second output of the program counter and through the fifth memory block is connected to the second input of the control unit. 2. The system according to claim 1, wherein the adaptive equalizer contains noise indicator, indication counter, divider, unit of reference signals, indicator of frequency characteristics, first and second permanent storage units, subtractors, counters, memory units, correction units, multiplier, synchronous detector and modulator, inverse fast Fourier transform and a fast Fourier transform unit whose outputs connected to the first inputs of the respective correction blocks, the outputs of which are connected to the inputs of the inverse fast Fourier transform unit and the inputs of the corresponding memory blocks, the outputs of which are connected to the first inputs of the respective subtractors, the outputs of which are connected to the first inputs of the counters, the first outputs of which are connected to the second inputs of the corresponding corrective blocks, the outputs of the block of reference signals are connected to the second inputs of the corresponding subtractors, the output of the divider is connected to the input of the display counter, the first outputs of which are connected with the second inputs of the respective counters, the second outputs of which are connected to the inputs of the frequency response indicator, the output of the inverse fast Fourier transform unit is connected to the first the input of the multiplier through a synchronous detector, the second input of which is connected to the output of the corresponding correction unit, the second. input of the multiplier is connected to the output of the first storage unit, the output of the indication counter is connected to the input of the noise indicator, the second output of the second subtractor is connected to the first input of the divider, the second input of which is connected to the second input of the second subtractor, the outputs of the modulator and the second persistent storage unit are connected respectively to the first and second inputs of the reference signal block, while the input of the fast Fourier transform block is the first input of the adaptive equalizer, the second input of which is the modulator input, the outputs of the correction blocks are the first outputs of the adaptive corrector, the second outputs of which are the third outputs of the counters, the output of the multiplier is the third output of the adaptive equalizer.