SU1728964A2 - Pulse repetition frequency multiplier - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing. The purpose of the invention is to improve the accuracy of the formation of the output frequency by using a ring of phase automatic frequency control. The device contains a clock pulse generator 1, the first element AND 2, a frequency divider 12 with variable division factor, output bus 22, storage register 11, control unit 3, input bus, first, second and third setters 5, 13 and 14 codes, counter 7 pulses, divider 9 codes, multiplexer 8, demultiplexer 10, adder 6, second element 15, first and second frequency dividers 4 and 16, frequency subtractor 17, third frequency divider 18, phase detector 19, low-pass filter 20 and controlled oscillator 21 pulses, 2 Il. s t

Description

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The invention relates to a pulse technique, can be used in automation devices, computer technology, in frequency converters and measurement technology, and is an improvement to the well-known multiplier according to auth. No. 1547050,

A digital periodic frequency pulse multiplier is known, comprising a clock pulse generator (GTI), a variable division frequency factor (DFD), a memory register, a frequency divider, a pulse counter, and a reset pulse driver.

However, such a multiplier has insufficient reliability due to the possibility of malfunctions at the time of its launch.

A periodic frequency pulse multiplier is known, comprising a GTI, DCDD, a memory register, a frequency divider, a pulse counter, a reset pulse shaper, the AND element, and a control pulse shaper. GTI is connected to the first input element And to the input of the frequency divider, the output of which is connected to the input of the pulse counter. The pulses of the input frequency are fed to the inputs of the reset pulse generator and the control pulse generator, to the input of the recording of the memory register. The output of the reset pulse generator is connected to the inputs of zero pulse counter and frequency divider. The output of the driver for control pulses is connected to the second input of the element I, and the output of the element I to the counting input of the PDKD, the output of which is connected to the output bus. The outputs of the pulse counter are connected through a memory register to the information inputs of the DPCD. At the output of the frequency multiplier, a sequence of pulses is formed with a frequency

Rvyh P FBX,

where n is the multiplication factor;

FBX - input frequency.

The disadvantage of the frequency multiplier is that it cannot be used as a tracking local oscillator in a digital tracking spectrum analyzer whose filtering channel uses narrow-band precision quartz or electromechanical filters with a center frequency of 8 or 128 kHz because it is impossible to add a constant frequency base to the output frequency .

The closest to the proposed one is a pulse multiplying frequency multiplier, containing a GTI, the first AND element, a control unit, a frequency divider, the first code master, an adder, a pulse counter, a multiplexer, a code divider, a de-multiplexer, a storage register, DDC, the second code master. the second element I.

GTI through the first element and connected

with the clock input of the PDCD, the output of which is connected to the output bus, and the information inputs are connected to the outputs of the storage register. The first input of the control unit

0 is connected to the input bus, the second input is connected to the output of the GTI, the clock input of the code divider and the input of the frequency divider, the output of which is connected to the first input of the second element I, the output of which is connected to

5 counting input of the pulse counter, the information inputs of which are connected to the outputs of the first code setter, the outputs - with the first group of multiplexer inputs, the outputs of which are with the first group of inputs

0 code splitter, the second group of inputs of which is connected to the outputs of the second code master, outputs - with the outputs of the demultiplexer, the first group of outputs of which is connected to the information ones

5 inputs of the storage register, the second group of outputs - with the first group of inputs of the adder, the second group of inputs of which is connected to the outputs of the third master code generator, the outputs - with the second group of inputs of the multiplexer. The first and second outputs of the control unit are connected to the second inputs of the first and second elements I, respectively, the third output is connected to the installation input of a pulse counter, the fourth

5 output - with the control input of the multiplexer, fifth output - with the trigger input of the code divider, sixth output - with the control input of the multiplexer and the seventh output - with the input of the storage register.

0 The control unit contains the first I element, the first input of which is connected to the first input of the control unit and to the second reset input of the pulse counter, the output to the clock inputs of the first and

5 of the second trigger, the inverse output of the first of which is connected to its information input, the direct output - to the information input of the second trigger, the inverse output of which is connected to the second input of the first element I, the direct output - to the information input of the third trigger, right my output is connected to the first output of the second element I, the output of which is connected to the counting input of the pulse counter, the outputs of which are connected to the address inputs of the storage device, the first to the fifth outputs of which are connected respectively about a second - sixth output of the control unit, a seventh output is connected to the clock input of the third flip-flop output and a sixth permanent storage device, a seventh output is connected to the second input of the second element I.

At the output of the device, a sequence of pulses is obtained with a frequency

M

in

n + fr

those. A constant frequency base is introduced into the output signal with the possibility of changing it over a wide range by changing the code supplied to the second group of inputs of the adder from the outputs of the first code generator.

A disadvantage of the known multiplier is the low accuracy of the formation of the frequency of the output pulses, due to the limited PDCD resolution and the error in measuring the input frequency. Such a multiplier cannot be used as the next local oscillator of a spectrum analyzer, in the filtering channel of which narrow-band filters (with a passband of from one to ten hertz) filters with a center frequency of 8 or 128 kHz are used.

The purpose of the invention is to improve the accuracy of the formation of the output frequency.

This goal is achieved by the fact that, in a pulse frequency multiplier containing a GTI, the first AND element whose output is connected to the output bus and the information inputs are connected to the outputs of the storage register, the control unit whose first input and output are connected respectively to the input bus and the first input of the first element And, the first, second and third setters of codes, pulse counter, informational inputs of which are connected to the outputs of the first setter of code, code divider, multiplexer, adder, second element of And and affairs frequency, the input and output of which is connected respectively to the output of the GTI and the first input of the second element And, the second input of which is connected to the second output of the control unit, the third output of which is connected to the installation input of the pulse counter, the counting input of which is connected to the output of the second element And outputs - with the first group of inputs of the multiplexer, the outputs of which are connected to the first group of inputs of the code divider, the second group of inputs of which are connected to the outputs of the second unit master of codes, the clock input - with the output of the GTI, the outputs - with the multiplexer inputs, the first group of outputs of which is connected to the information inputs of the storage register, the second group of outputs - from the first

a group of inputs of adders, the second group of inputs of which is connected to the outputs of the third code master, the outputs with the second group of inputs of a multiplexer, the control input of which is connected to the fourth output of the control unit, the fifth, sixth, seventh outputs of which are connected to the outputs of the triggering of the code divider, control of the demultiplexer and recording of the storage register, entered between the output of the GTI and the second input of the first element AND the circuit of the serially connected second frequency divider, subtractor of frequencies, the second input to expensively connected to

5 output bus, third frequency divider, phase detector, the second input of which is connected to the input bus, low pass filter, controlled by GTI.

Comparison of the proposed technical

0 solutions with others shows that frequency dividers and subtractors, as well as PLL systems containing a phase detector, a low-pass filter, a control element, and a tunable oscillator, are known.

However, when these blocks are used in the digital pulse frequency multiplier to compensate for the rio’s error in the output signal, they exhibit

0 new properties, which leads to an increase in the accuracy of formation of the output signal. At the same time, the output signal of the frequency multiplier is synthesized to the phase in accordance with the expression

5Рвых П F ex + Fn

Thus, it becomes possible to use the proposed multiplier as a digital heterodyne of a tracking spectrum analyzer, which contains narrow band-pass filters,

Fig. 1 is an electrical block diagram of the proposed multiplier; 2 is a control unit.

The multiplier contains a generator of 1 or 5 pulses, the first element I 2, the control block 3, the first divider 4 frequencies, the first presetter 5 code, the adder 6, the counter 7 pulses, multiplexer 8, divider 9 codes, demultiplexer 10, register 11 storage 0 NDT, 12, the second unit of the 13 code, the third unit of the 14 code, the second element And 15, the second frequency divider 16, subtract 17 frequency frequencies, the third frequency divider 18, phase detector 19, low-pass filter 20 and 5 controlled pulse generator 21 . A clock pulse generator 1 through a second frequency divider 16, a frequency subtractor 17, a third frequency divider 18, a phase detector 19, a low-pass filter 20, a controlled pulse generator 21, and a first

element 2 is connected to a clock input of a divider 12 with a variable division factor, the output of which is connected to the output bus 22 and the second input of the frequency subtractor 17, and the information inputs are connected to the outputs of the storage register 11.

The pers input of the control unit 3 is connected to the input bus 23 and to the second input of the phase detector 19, the second input to the output of the clock generator 1, to the clock input of the divider 9 codes and to the input of the frequency divider 4, the output of which is connected to the first input of the second element 15 The output of which is connected to the counting input of the pulse counter 7, the information inputs of which are connected to the outputs of the first unit 5 of the code, the outputs to the first group of inputs of the multiplexer 8, the outputs of which are connected to the first group of inputs of the divider 9 codes, the second the input group of which is connected to the outputs of the second unit 13 of the code, the outputs to the inputs of the demultiplexer 10, the first group of outputs of which is connected to the information inputs of the storage register 11, the second group of outputs to the first group of outputs of the adder 6, the second group of inputs to which are connected to the outputs the third setting unit 14 of the code, the outputs - with the second group of inputs of the multiplexer 8. The first and second outputs of the control unit 3 are connected to the second outputs of the first 2 and second 15 And elements, respectively, the third output of which is connected to tanovochnym input pulse counter 7, the fourth output - to an input of a control multiplexer 8, a fifth output - to the input of the divider 9 start codes, the sixth output-control input demultiplek- with litter 10 and the seventh - to the input of the register 11 storing recording.

The control unit 3 contains the first element AND 24, the first input of which is connected to the first input of the control unit 3 and to the reset input of the pulse counter 25, the output to the clock inputs of the first 26 and second 27 triggers, the inverse output of the first of which is connected to its information input, direct output - to the information input of the second trigger 27, the inverse output of which is connected to the second output of the first element I 24, direct output - to the information input of the third trigger 28, the direct output of which is connected to the first output of control unit 3, Torah output of which is connected to a first output of the second AND gate 29, the output of which is connected to the counting input of the counter 25 pulses, the outputs of which are connected with the address inputs of PROM device

30, the first to fifth outputs of which are connected respectively to the second to sixth outputs of the control unit 3, the seventh output of which is connected to the clock inputs of the third trigger 28 and to the sixth input of the permanent storage device 30, the seventh input of which is connected to the second input of the second element 29 .

The generator 1 clock pulses is built according to the scheme of a multivibrator on TLL inverters with quartz frequency stabilization. The first element And 2, the second element And 15, the first 5, the second 13 and the third 14 prescalers code built on the chip

5 K155LAZ. The dials 5, 13, and 14 of the code are designed so that at their outputs, after power is turned on, a binary number is established, and the voltage values for the zeros and ones of this binary number correspond to TTL levels.

The control unit 3 is built on the K155TM7, K155LAZ, K155IE7 and K155PE: 3 chips.

First 4, second 16, third 18 dividers

5 frequencies, a counter of 7 pulses, PDKD 12 are made on the basis of the K155EI7 counters, the adder 6 - on an ALU K155IPZ microcircuit.

Multiplexer 8 is made on the basis of K155LAZ microcircuits in such a way that when

0, supplying a control signal to the control input at the output of multiplexer 8, the information present on one of the output buses appears, depending on the level of the logical signal at the control 5 input of multiplexer 8.

The demultiplexer 10 is made on the basis of a K155LAZ chip, so that when a signal is sent to the control input, the information present at the input of the switch,

0 is transmitted to one of the output buses, depending on the level of the logical signal at the control input of the demultiplexer 10. The divider 9 codes are made on the basis of a sequential multiplier-divider

5 КР1802ВР2.

Storage register 11 is implemented on K155IR13 chips (universal 8-bit shift registers).

Controlled pulse generator 21 and

The 0 phase detector 19 is made on the basis of a 564GP PLL chip, the low pass filter 20 is proportional to the integrating circuit consisting of two resistors and a capacitor.

5 The subtractor of 17 frequencies is built on a well-known scheme.

The multiplier works as follows.

In the initial state, the first output of block 3 is set at a low level (at

the block diagram of the initial installation circuit is conventionally not shown), as a result of which element 2 is closed at the second input, pulses from the generator 21 output to the clock input of the divider 12 are not received, counter 25 is reset and the code corresponding to the zero address is set at the output of the memory 30. Upon the arrival of the second pulse to the bus 23, the flip-flop 27 switches to one state and the low level signal from the inverse output of the trigger 27 prohibits the input signal from passing to the clock inputs of the flip-flops 26 and 27. On the arrival of the thirty-second clock pulse from the generator output 1 An individual signal drop at the sixth output of the memory 30 switches the trigger 28 to a single state. This signal at the first output of block 3 opens element 2 at the second input and pulses from the output of generator 21 are fed to the input of divider 12, with the result that a signal with frequency Pout is generated on bus 22. A delay after switching on is necessary to prevent the occurrence of a false frequency at the output of the multiplier at the first moment after turning on the power.

Thus, after the first two pulses of the input frequency and thirty-two pulses of the clock frequency, the register 11 stores the correct number that determines the input frequency of the division, and therefore also the frequency at the output of the multiplier.

Programming map of storage device 30 is shown in the table.

Consider the operation of the multiplier after the arrival of the i-ro impulse of the input frequency to the bus 23. To the input of the divider 4 frequencies with a division factor equal to n, pulses come from the output of the generator 1. With the arrival of the first clock pulse after the front of the i-ro pulse of the input frequency at the second output of block 3, a low level appears; the closing element AND 15. The pulses of the 4 frequency divider do not arrive at the counting input of the counter 7, as a result of which a number equal to

g vx P

where RT-clock frequency at the output of the generator;

FBX - input frequency on the bus 23;

n is the division factor of the divider 4 frequencies.

At the same time, a high level appears at the fourth output of block 3, which corresponds to the multiplexer connecting 8 outputs of the counter 7 to the first group of inputs of the divider 9 codes. Positive differential

the signal at the fifth output of block 3 starts the divider 9 of the codes, which is clocked by the pulses of the generator 1 and divides the binary code of the number 1 supplied from the outputs for the sensor 13 of the code into the second group of inputs of the divider 9 of the codes by the number N, i.e. after fourteen clocks, the output of divider 9 has a code equal to N 1 / N.

The demultiplexer 10 is turned on by the signal from the sixth output of block 3 so that the outputs of divider 9 are connected to the first group of inputs of the adder 6, to the second group of inputs of which the code of the number a from the outputs of the setter 14 is fed, and a Fn / FT.

Thus, at the outputs of the adder 6, a code equal to 1 / N + a is obtained.

Upon the arrival of the last clock pulse of the first division cycle, the multiplexer 8 switches so that the outputs of the adder 6 are connected to the first group of inputs of the divider 9. At the same time, the third input of the block 3 shows a low level, which records the code from the output of the setpoint 5 in counter 7. This pre-recording is necessary to take into account in changing the period of the input frequency of the time when the counter 7 is stopped. Upon the arrival of the next clock pulse, a high level appears at the second output of the block 3 and the counting pulses through the element 15 begin to flow to the counting input of counter 7. At the same time, the second division cycle starts, after which the code 9

1 1FT

M

A + a

F I n F F p FTFT

n F n

At the moment of arrival of the last clock pulse of the second division cycle, the low level at the sixth output of block 3 switches the demultiplexer 10 so that the outputs of the divider 9 are connected to the information inputs of the register 11, which is written to the next signal of the clock pulse with a positive differential signal at the seventh output of the block 3. Divider 12 divides the frequency by the code M. Thus, at the output of the multiplier, a sequence of pulses is obtained with the frequency

Pvyh PPG p + Fn.

Due to the limited size of the splitter 12 and the measurement error of the input frequency, the output signal of the multiplier is generated with an error DS

Pvyh FBX P + Fn + A F.

To eliminate the frequency error, the DRsignal Pout is fed to the second input of the subtractor 17 frequencies. A signal with a frequency of the base Fn FT / K is output to its first input from the output of the second frequency divider 16, which has a division factor k.

The output of the subtractor 17 frequency signal is generated

RV FBX n + A R.

From the output of the third frequency divider 18 with a division factor n, the signal with the frequency Pf Pin + AF / n is fed to the first input of the phase detector 19, to the second input of which the signal is fed with the frequency FBx. The voltage at the output of the phase detector 19 depends on the phase shift between the input signals, as a result of which the output of the filter 20 generates a signal proportional to the error AF / n, which is fed to the input of the controlled oscillator 21, changing its output frequency so that the frequency error And Rna output is minimal.

0

five

0

five

Thus, at the output of the multiplier receive a sequence of pulses with a frequency

Rvyh Rvh p + pn, i.e. A constant frequency stand is introduced into the output signal with the possibility of changing it over a wide range by changing the code supplied to the second group of inputs of the adder 6 from the outputs of the setter 14.

FORUMAWLAH AND ISLANDS

Pulse Frequency Multiplier by auth. No. 1547050, characterized in that, in order to improve the accuracy of the output frequency, it includes serially connected second frequency divider, frequency subtractor, third frequency divider, phase detector, low-pass filter and controlled pulse generator connected between the clock generator and the second input of the first element And, while the second input of the subtractor frequency is connected to the output bus, and the second input of the phase detector with the input bus.

FIG. I

Claims (1)

10 FORMULA AND PORTRAIT Pulse repetition rate multiplier No. 1547050, characterized in that, in order to increase the accuracy of generating the output frequency, 15 a second frequency divider, a frequency subtractor, a third frequency divider, a phase detector, a low-pass filter and a controlled pulse generator, included 20 between the clock pulse generator, are introduced into it and the second input of the first element And, while the second input of the frequency subtractor is connected to the output bus, and the second input of the phase detector is connected to the input bus.