SU1728861A1 - Device for performing vector and scalar operations on real numbers - Google Patents

Abstract

The invention relates to computing and can be used in universal and specialized methods. Xi and Ui - in numeral systems for hardware implementation of vector-scalar operations Y1b {1, 2L} (L is the number of components of the vector operand) for real numbers, -represented in additional code in fixed-comma form. The purpose of the invention is to expand the functionality of the device by performing an operation Xi of the form Ui Y. The goal is achieved by the introduction of an auxiliary operation unit and the element UNIMQUALITY in the device containing (L + 1) operating units and the control unit. 2 hp f-ly, 6 ill. cl

Description

,, Xi

of type l) -j

The invention relates to computing and can be used in universal and specialized computer systems for the hardware implementation of vector-scalar operations.

Y It {1,2 L} (L-number

components of the vector operand) for real numbers represented in the additional code in the form of a fixed comma.

A device for performing multiplication and division operations is known, comprising a receiving and outputting unit, a register, a summing unit, a multiplexer, a control unit, an activity sign generating unit, a trigger, a cycle counter, a decoder, a switch, NOT elements, AND, OR, 2-OR and UNEQUALITY with appropriate links.

The disadvantages of the known device are low speed and limited functionality, providing simultaneous processing of only two operands, which must be positive. In addition, the known device does not allow the multiplication and division operations to be performed at the same time.

The closest to the proposed technical entity is a device for parallel division of numbers, containing (L + 1) operating units, a control unit, and a sign trigger. The disadvantage of this device is its limited functionality that ensures only a division operation.

vj KE 00 00

ABOUT

The purpose of the invention is to expand the functionality by performing an operation of the form Ui -j-Y,

The goal is achieved by the fact that a device for performing vector-scalar operations on real numbers, containing (L + 1) operating units (L is the number of components of the vector operand) and a control unit, with the input of the 1st component of the vector operand device (Vlt {1,) is connected to the first information input of the 1st operational unit, the first output of which is connected to the output of the 1st component of the result vector of the device, and the second output to the output of the 1st sign of the device overflow connect The first information input () of the operation unit, the first output of which is connected to the input of the divider characteristic of the control unit, the start input and the clock input of which are connected to the start input and the clock input of the device, respectively, the output of the sign of dividing by zero the output of the control unit, the second output of which is connected to the output of the sign of the end of the operation of the device and the input of the resolution resolution of each operation unit, the information input of each operation unit is connected to the third output The control unit, the fourth output of which is connected to the recording resolution inputs of all operational blocks, is additionally introduced an auxiliary operational block and an unequal element, the output of which is connected to the sign-forming input of the 1st operational block, the sign-forming input of the () -th operational block is connected with the input logic zero of the device, the input of the multiplier is connected to the input of the multiplier feature of the control unit and the first information input of the auxiliary operation unit, the second information input The input of which is connected to the inputs of the device divider and the control unit, the input of the intermediate code of which is connected to the output of the auxiliary operating unit and the third information inputs of all the operating units, the input of the sign of multiplying by zero which is connected to the fifth output of the control unit, the second, third and the fourth outputs of which are connected respectively to the account resolution input, the third information input and the recording resolution input of the auxiliary operation unit, the divider input of which is connected with

the output of the () -th operational unit, the inputs of the sign bits of the multiplier and the divider of the device are connected respectively to the first and second inputs of the UNEMINABLE element,

The goal is also achieved by the fact that the operational unit contains two modulo-2 adders, a multiplexer, a register, a shifter, two AND elements, an OR element, a UNIMINARY VARIABLE, an adder and an NOT element, the output of which is connected to the second output of the block, the first output of which is connected to the output of the first element, And, the first inverse input of which is connected to the input of the sign of multiplying by zero the block, the second information input of which is connected to the shift control input of the shifter, the information input of which is connected to the output register tra, the input of the first adder adder and the second input of the first element I, the outputs of the sign bits of the register are connected to the first and second inputs of the UNIFORM VALUE, the output of which is connected to the input of the element NOT and the first input of the OR element, the second input of which is connected to the third information input of the block and the input of the first addend of the first adder modulo 2, the input of the second addend of which is connected to the output of the shifter, and the output to the input of the second addend of the adder, the output of which is connected to the first information input ohm multiplexer, the second information input of which is connected to the output of the second modulo-2 adder, the inputs of the first and second terms of which are connected respectively to the sign-forming input and the first information input of the block, the count resolution input of which is connected to the third input of the OR element and the control input of the multiplexer, the output of which is connected to the information input of the register, the recording input of which is connected to the output of the second element And, the first and second inputs of which are connected respectively to the enable input audio recording unit and the output OR gate.

The goal is also achieved by the fact that the auxiliary operational block contains three modulo 2 adders, two adders, a multiplexer, a register, a shifter and an element, whose output is connected to the input of the first addend of the first modulo-2 adder, the second addend of which is connected to the output of the shifter , the shift control input and the information input of which are connected respectively to the third information input of the divider unit, the first and second information inputs of which are connected respectively to the inputs of The second and third adders modulo 2, the outputs of which are connected respectively to the inputs of the first and second terms of the first adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the second adder, the input of the first term of which is connected to the output of the first adder modulo 2, and the input of the second term to the input of the element NOT, the output of the block and the output of the register, whose information input is connected to the output of the multiplexer, which controls od which is connected to the input authorization unit accounts write enable input is connected to the input of register entries.

The operation of the device is based on the use of an iterative algorithm that implements a multiplicative calculation method. The operands and the result are represented as (n + 1) -bit numbers in the additional code in fixed-point form. In the most significant (zero) bit, the sign code of the number is written, bits from the first to the nth are numeric.

Xi (| t {1,2L})

Y ,, 1.

The operation is performed using recurrence relations:

f ak ak-1 - Skbk-1 bk bk-1 + Skbk-1 2 Jk;

VKt {1,2t} Cik Cik-1 + SkCik-1.

jCLk CLk +: SkCtK -2, (1) where k is the number of the iteration being performed,

tЈ {1, 2, ..., n} is the number of iterations necessary to obtain the results of the operation.

The value of Sk is determined by the most significant (zero) bit of the operand aic-1, Sk sgnak-i 1-2 -aic-i (0).

The jk values in the execution of the kth iteration are selected on the basis of the ratios:

jk jjk -jk2 with jk1 jk2I

| jk-l (0) npnjk jk2. (2)

where jki min {Jc N / aic-i (l) ak-i (0)},

Jk2 min {jЈ N / bk-iG) 1} ak-i (0) is the value of the zero (sign) digit of the code ak-1.

The initial values of the variables are determined by the ratios:

aO IYi - / Zj; bo / Z /; J lt {1, 2 ..... L};

 sgnZ Xi. (3)

Calculations continue until the condition of the next tth iteration is satisfied

Claims (3)

I atl. (4) where m is the multiplicative resolution of the calculations, which provides the result with a given accuracy (m n). The resulting tth iteration ait values are used in as a result of the operation Ui. Figure 1 shows the structural diagram of the device; Fig.2 - structural scheme operating unit; Fig. 3 is a block diagram of the auxiliary operational unit; Fig. 4 is a block diagram of the control unit; FIG. 5 is a functional diagram of a control signal generation unit; FIG. 6 is a functional diagram of the control code generation unit. The device contains (L + 1) operating units 1, auxiliary operating unit 2, control unit 3, element INEQUALITY and has input 5 multiplier, start input 6, clock input 7, divider input 8, L inputs 9 components of the vector operand, output 10 of the characteristic End of operation, output 11 of the characteristic Division by zero, L outputs of 12 components of the vector result, L outputs 13 of the characteristic overflow. The operating unit contains an adder 14 modulo 2, a multiplexer 15, a register 16, a shifter 17, an adder 18 through. module 2, the adder 18, the adder 19, the element OR 20, the element And 21, the element EQUITY 22, valve circuit 23, the element is NOT 24 and has the first 25, the second 26, third 9, fourth 27, fifth 28, sixth 29 and seventh 30 inputs, the first 12 and second 13 outputs. Auxiliary operating unit contains adders 31 and 32 modulo 2, adder 33, multiplexer 34, register 35, shifter 36, NOT element 37, adder 38 modulo 2, adder 39 and has first 40, second 41, third 5, fourth 8, fifth 42 and sixth 43 entrances and exits 44. The control unit contains nodes 45 and 49 of forming the number of the highest unit, a shifter 46, a node 47 of forming the control code, an adder 48 modulo 2, the control signal generation unit 50 has the first 51, the second 52, the third 6, the fourth 7, the fifth 8 and the sixth 5 inputs and the first 53, the second 54, the third 10, the fourth 11 and the fifth 55 outputs. The control signal generation node contains two elements AND 56, four elements 57, two triggers 58 and has the first 6, second 7, third 53, fourth 8, fifth 5 entrances and the first 54, second 10, third 11 and fourth 55 exits. The control code generation unit contains two elements OR 60 and two instances AND 61 and has first 62 and second 63 inputs and output 53. The device works as follows. In the initial state, v It {I, 2, ..., L} is fed to the input 9.1 of the device and then the value of the XI element arrives at the third input of the operation unit 1.1. The input of the device 5 receives the value of the multiplier, and the input 8 - the value of the divider Z. The clock pulses (TI) are continuously received at the input 7 of the device. Symptom The end of the operation, coming from the third output of the control unit 3 to the fourth input of each operational unit 1, the fifth input of the auxiliary operational unit 2 and to the output 10 of the device, has a single value. Information codes arriving at the third inputs of the operating units 1 are converted from (n + 1) -disable to (V + 2) -digit format (Vt) by splitting the sign bit to use in the calculations of the modified additional code, as well as the addition of (V - n) low-order numeric bits, which are assigned a zero value. Changing the format of the operands is carried out in order to simplify the detection of a possible overflow of the discharge grid in the course of calculations, as well as to ensure the allowable error of calculations arising from the truncation of numbers shifted during calculations beyond the limits of the discharge grid. In addition, the use of additional bits makes it possible to realize a change in the sign of a number by inverting it without subtracting the unit to the least significant bit. To start the calculations synchronously with one of the TIs, the Start signal is sent to the input 6 of the device. The Start signal at the second output of the control unit 3 generates the Signal signal, which is fed to the fifth inputs of the operating units 1 and to the sixth input of the auxiliary operating unit 2, ensuring that operands to their third inputs are inserted into the specified operating units. From the output of the auxiliary operation unit 2, the code ao, containing the sign and m most significant numeric bits of the code ao, is fed to the second input of the control unit 3. If all bits of the code ao are equal to zero or all are equal to one, the sign End of operation saves a single value and no calculations are performed. The unit value of the feature End of the operation is also saved with zero values at input 5 or at input 8 of the device, where the multiplier and divisor codes, respectively, arrive. At zero values of all bits of the code received at the input 5 of the device and further to the sixth input of the control unit 3, at the fifth output of the unit 3 a single value of the attribute Multiplication by zero is formed. At the same time on the first output of the 1st transaction block lt {1, 2 L} produces a zero result value. At zero values of all bits the code received at the input 8 of the device and further to the fifth input of the control unit 3, at the fifth output of this block and further at the second output 11 of the device, the unit value of the sign Divide by zero is formed. If there is at least one unit and at least one zero in the numerical bits of the code arriving at the second input of control unit 3, and different from zero code values arriving at inputs 5 and 8 of the device, the sign End of operation generated at the third output 3 control unit, takes a zero value and the device performs an iterative calculation process in accordance with (1). The next k-iteration fkt {1, 2,.,., T} is implemented in the device as follows. The first and second inputs of the control unit 3 are received from the first output of the operating unit 1.L + 1, the values of bk and from the output of the auxiliary operating unit 2, the values of ak, respectively. In accordance with (2), (t + 1) -discharge is formed at the first output of the control unit 3 unitary code 3k, containing a single value in the jkth bit and zero values in the remaining bits, which is fed to the first inputs of all operation units 1 and the auxiliary unit 2. In accordance with (1) operational unit 1.1 (i7U- {1, 2L}) forms the value of C || , the operational block 1.L + 1 is the value of bk, the auxiliary operational block 2 is the value of ak. With the arrival of the next TI, a signal is generated at the second output of the control unit 3. The signal arrives at the fifth inputs of the operation units 1 and the sixth input of the auxiliary operation unit 2. The value of ak, bk and Cik (rlt {1,2L}) on the registers of the auxiliary operation unit 2, the operation unit 1 .L + 1 and the operation unit 1.1 (1 (-. {1, 2L}, respectively. If during the calculation in the operation block 1.1 lt {1, 2, .... L}, as a result of the next iteration, an overflow of the discharge network occurs, the second output of the operation block 1.1 after the end of the iteration will generate a single value of the Overflow feature that will be saved before the next operation. At the first output of the operation unit 1.1, the result of the iteration, in the implementation process of which the overflow has occurred, will be generated and will remain until the start of the next operation. The iteration process continues until, as a result of the implementation of the next tth iteration, all (t + 1) bits of the code arriving at the second input of control unit 3 will simultaneously be equal to zero or simultaneously equal to one. In this case, the control unit 3 will stop the formation of the Signing signals at its second output and form a single value of the attribute End of operation at its third output. At the end of the calculations, the value of the 1st element of the result vector U will be generated at the first output of the operation unit 1.1 li- {1, 2, ..., L}. Operational block 1.lv lc {1, 2, .... L} works as follows. In the initial state, the inputs 25, 26, 9, 27, 28, 29 and 30 receive the values of the unitary code Jk, the result of adding modulo 2 digits of the multiplier and divisor Cio sign End of operation, Signal input, value (0), sign Multiply by zero, respectively. The value of CIQ arriving at input 9.1 of the block is added modulo 2 with the value present at input 26, modulator 2 admittance 14. Single characteristic value End of operation from input 27 of the block to the control input of multiplexer 15 ensures that the incoming code passes from the output of the adder 14 modulo 2 to the second information input of the multiplexer 15, to its output and further to the information input of the register 16, and also generates a single signal at the output of the element OR 20, ensuring the passage of a signal. through the AND gate 21 to the control input of the register 16. As a result, a single feature value End Storing operation performs signal entering an initial value of the variable, the processing unit 1.1.k When executing the kth iteration, i / kt {1, 2, .., t} value СЈ, -..-. Ј.Ј {1, 2, .., L} from the output register 16 is fed to the second input of the shifter 17, as well as to the second input of the adder 19. At the first input of the shifter 17 comes the unitary KOflJk. The shifter 17 provides a shift of information arriving at the second input towards the lower bits by the number of bits equal to the number of a single bit in the unitary code received at the first input with the reproduction of the left bit cleared during the shift. As a result, at the output of the shifter 17, the code Ci | , which the comes to the first input of the adder 18 modulo 2, for each bit of the second input of which the value of the zero (sign) code ak-1 is applied. As a result, the value of SkCik is generated at the output of the adder 18 modulo 2, which is fed to the first input of the adder 19. At the output of the adder 19, the value of the sc is received in accordance with (4), fed to the first information input of the multiplexer 15. The zero value of the feature End of operation ensures the passage Ci code | to the output of the multiplexer 15 and further to the information input of the register 16. The sign bits of the Cik- code: from the output of the register 18 are fed to the inputs of the Equivalence element 22. If the sign bits of the Cik code coincide, which corresponds to no overflow as a result of the previous iteration, the output of the EQUIVALITY element 22 is formed by a single signal level, which through the OR element 20 passes to the second input element And 21, ensuring the passage through the element And 21 signal Sign, arriving at its first input. If the sign bits of the code C do not match, || - t, which corresponds to the presence of overflow as a result of the previous iteration, at the output of the element EQUITY 22 a zero signal level is formed. If the value of the sign (zero) digit of the code present at the second input of the element IL-20 is present ak-1 is also zero; at the output of the element OR 20, a zero signal is generated, which blocks the passage of the signal. Entering through the element 21 and 21 at the zero value of the attribute End of operation. In register 16, there remains the information recorded as a result of the implementation of the iteration, during the execution of which an overflow of the discharge grid occurred. The signal from the output of the EQUITY 22 element through the NOT element 24 also goes to the output 13 of the block as a single value of the Overflow characteristic. With a single level of the signal at the output of the element OR 20, the next signal. The recording arriving at the input 28 of the block passes through the element 21 of the control input of the register 16, recording the value of Sc in the register. At the end of the calculations, the value C | $ generated as a result of the execution of the tth iteration as a result of Ui comes from register 16 through gate circuit 23 to output 12.1 of the block. If there is a single value at the output 30 of the Multiplication by zero input to the second inverse input of the gate circuit 23, the zero value of the result Ui is formed at its output. At the same time, the execution of the kth iteration is completed. Operational block 1.L + 1 processes the variable bk-1 in the same way as described. The difference lies in the formation of the initial value with the variable processed in this block. In this case, the value of logical zero is input to input 26, and the value bo is input to input 9. Auxiliary operating unit operates as follows. In the initial state, the inputs 40, 41, 5, 8, 42, and 43 of the block receive the values of the unitary code Jk, the value of bk-1, the value of the multiplier Y, the value of the divisor Z, the sign of the end of the operation and the signal of the entry, respectively. The second input of the adder 31, modulo 2, receives a (Y + 2) -digit code containing the sign code of the multiplier Y, n numeric bits of the multiplier Y code and (V-n) zeros in the lower order bits. At the first input of the adder 31 modulo 2 receives the sign code of the multiplier. As a result, at the output of the adder 31 modulo 2 a multiplier module code is generated, which is represented with precision. Similarly, at the output of the adder 32 modulo 2, the code of the divider module is presented, represented as a multiplier with an accuracy. From the output of the adder 31 modulo 2, the multiplier module code arrives at the first input of the adder 33, the second input of which from the output of the adder 32 modulo 2 receives the inverse code of the divider module. Thus, at the output of the adder 33, the initial value of ao is formed, which is then fed to the second information input of the multiplexer 34. Single value of the sign End of operation, coming from input 42 to yrt the main input of the multiplexer 34, ensures the passage of the code AOS of the second information input of the multiplexer 34 to its output and further to the information register input 35. As a result, with a single value of the sign END OF THE OPERATION signal Entry ensures that the value of ao is entered into register 35. When the kth iteration is performed, r {1, 2, ..., t} is ak-1 0 from the output of the register 35 is fed to the second input of the adder 39, the first input of which receives the value from the output of the adder 38 modulo 2. The adder 33 modulo 2 provides bitwise modulo addition .5 2 values arriving at its first input from the output of the shifter 36 with the inverse value of the most significant sign bit ak-i (O). The value ak-i (0) comes from the output of the NOT 37 element, the value at the input of which comes from the output of the sign (zero) bit of the register 35. At the first input of the shifter 36 from the input 40 of the block, the unitary signal is supplied, to the second input from the input 41 blocks - the value of the code bk-1. The shifter 36 provides the shift 5 to the right of the code arriving at its second input, for the number of bits equal to the unit number in the unitary code 3k. The leading zero bit of the shifted code in this case multiplies. As a result, the output 0, the shifter 36 generates the code bk-1. At the output of the adder 33, the value ak ay -; Sk bk-1 is received at the first information input of the multiplexer in accordance with expressions (1) 5 34. The zero value of the feature. End of operation ensures the passage of the code ak to the output of multiplexer 34 and further to the information input of the register. At the signal “CURRENT” this code is written into register 35 and is outputted at output 44 of the block, The control unit operates as follows. The inputs 51, 52, 6, 7, 8, and 5. receive the values bk-1, ak-1, the START signal, TI, code 5 divider Z and code multiplier Y, respectively. The adder 48 modulo 2 forms at the output the absolute value of the code ak-1 arriving at its first input by incrementing modulo 2 0 of each bit of a code with a sign (zero) bit of this code, which is supplied to the second input of modulator 48 modulo 2. The value from the output of adder 48 modulo 2 is fed to the input of node 49 of the formation 5 numbers of the highest unit. The input of the node 45 forming the number of the highest unit receives the value of bk-1. Nodes 45 and 49 form unitary codes containing a unit in the bit whose number is equal to the number of the highest unit in the code present at the input of each node. The first control input of the shifter 46 receives a unitary code from the output of node 45, providing a left shift by a number of bits equal to the number of a single bit j in this unitary code of another unitary code coming from the output of node 49 to the second information input of the shifter 46. Thus, at the output of the shifter 46, a unitary code is formed containing a unit in the discharge, the number of which is equal to the difference of the numbers of the upper-order bits in the codes a | c-1 and bk-1, respectively. In the event that the JK-number, the most significant bit of the code is less than or equal to the number of the jky-high single bit of the bk-1 code, the output of the shifter 46 generates a code containing all zeros. The code thus generated is fed to the first input of the control signal generation section 47 of the code, to the second input of which the zero (sign) bit of the code aa is applied. At the output of the node and then at the first output 53 of the block, a unitary code 3k is formed in accordance with (2), which determines the magnitude of the shift jk. At outputs 54, 10, 11 and 55 blocks, the Signal input signal, the End of operation sign, the Division by zero sign and the Multiplication by zero sign are formed respectively. The control signal generation unit operates as follows. The inputs 6,7,59,8 and 5 receive the signal START, Tl / l, m of the higher numeric bits of the code / ak-1 (n + 1) times the rank code of the divider Zn (n + 1) -digit code of the multiplier respectively. If all the inputs of the first element And 56 have zero values, a single value is formed at its output, which the passage through the second element OR 57 enters the output 10 of the node as a sign of the end of the operation, as well as the second inverse input of the second element And 56, blocking the passage through him ti. The third and fourth elements OR 57 form single values at their outputs if their inputs contain only zero value. The values from the outputs of these elements are fed to the information inputs of the first and second triggers 58, respectively. The second control inputs of these triggers are given a START signal from input 6 of the node, ensuring that the generated characteristic values are stored. Divide by zero and Multiply by zero, respectively, at the moment the operation starts and save these signs until the next START signal appears. Values from the outputs of these triggers are fed to the outputs 11 and 55 of the node, as well as to the second and third inputs of the second element OR 57, forming the corresponding value at its output sign End of operation. The appearance at the first input of the first element OR 57 of a single value of the trigger signal ensures that a signal is generated at its output. can then be formed on the basis of TI at the zero value of the sign End of operation. The Signal signal in the second case is formed at the output of the second element And 56 and further through the second input first element OR 57. The node forming the control code works as follows. The inputs 62 and 63 are supplied with the values of the m-bit unitary code and the value zero sign bit code ak-1, respectively. If there is a code at input 62 that contains only zero values, the output of the first element OR 60 forms a single value that goes to the first input of the first And 61 element, to the second input of which the value of the zero (sign) code ay is applied . Thus, the magnitude of the shift jk will be formed in accordance with (2). The second element And 61 forms a single value in case if only zero values are present at inputs 62 and 63, which corresponds to the situation jK-,  jk2 and ak-i (O) 0. At the same time, the unitary code 3k contains a one at zero bit, which determines the transmission of information without shifting. So the positive effect The proposed device consists in extending the functionality. Formula 1 and 1. A device for performing vector-scalar operations on real numbers, containing (L + 1) operational blocks (L is the number of components of the vector operand) and a block control, with the input of the 1st component vector operand of the device (Wt {1, 2 L}) is connected to the first information input of the 1st operational unit, the first output of which is connected to the output of the 1st component of the device result vector, and the second output to the output of the 1st sign of the device overflow, the input of the device divider is connected to the first information input ( L + 1) -rp operating unit, the first output of which is connected to the input the control unit divider sign, the start input and the clock input of which is connected to the start input and the clock input of the device, respectively; the output of the divide sign of zero is connected to the first output of the control unit, the second output of which is connected to the output of the sign of the operation end of the device and the account enable input of each operational unit, the second information input of each operation unit is connected to the third output of the control unit, the fourth output of which is connected to the recording enable inputs of all operations these blocks, characterized in that, in order to extend the functionality by performing an operation of the form Ui y-Y, the auxiliary operational block and the UNEQUALITY element are entered, the output of which is connected to the input of the sign maker of the 1st operational block, the input of the formation of the (L + 1) -ro sign of the operational block is connected to the input of the logical zero of the device, the input of the multiplier of the control block and the first information input of the auxiliary operation unit, the second information input of which is connected to the inputs of the device divider and the control unit, the input of which intermediate code is connected to The output of the auxiliary operation unit and the third information inputs of all operation units, the input of the multiplier by zero attribute of which is connected to the fifth output of the control unit, the second, third and fourth outputs of which are connected respectively to the account resolution input, the third information input and the recording resolution input of the auxiliary operating unit whose input of the divider is connected to the output of the () -th operational unit, the inputs of the sign bits of the multiplier and the device divider are connected respectively to the transducer th second inputs and unequal element. 2. The device according to claim 1, that is, with the fact that the operational unit contains two modulo-2 adders, a multiplexer, a register, a shifter, two AND elements, an OR element, an EQUIVALENCE element, an adder and an element NOT, the output of which is connected to the second output of the block, the first output of which is connected to the output of the first element I, the first inverse input of which is connected to the input of the sign of multiplying by zero the block, the second information input of which is connected to the shift control input of the shift, the information input of which is connected to re exit the gistra, the input of the first term of the adder and the second input of the first element I, the outputs of the sign bits of the register are connected to the first and second inputs of the UNIFORM element, the output of which is connected to the input of the element NOT and the first the input of the OR element, the second input of which is connected to the third information input of the block and the input of the first term of the first modulo-2 adder, the input of the second term of which is connected to the output the shifter, and the output is the input of the second term of the adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the second modulo 2, the inputs of the first and second terms of which are connected respectively to the input of the formation of the sign and the first information input of the block, the input of the resolution of which is connected to the third input of the OR element and the control input of the multiplexer, the output of which is connected to the information input. a register whose recording input is connected to the output of the second element AND, the first and second inputs of which are connected respectively to the recording enable input of the block and the output of the OR element. 3. Pop-up device 1, characterized in that the auxiliary operation unit contains three modulo-2 adders, two adders, a multiplexer, a register, a shifter and a NOT element, the output of which is connected to the input of the first term of the first modulo-2 adder, connected to the output of the shifter, the input of the shift control and the information input of which is connected respectively to the third information input and the input of the divider unit, the first and second information inputs of which are connected respectively to the inputs and the terms of the second and third adders modulo 2, the outputs of which are connected respectively to the inputs of the first and second components of the first adder, the output of which is connected to the first information input of the multiplexer, the second information input of which is connected to the output of the second the adder, the input of the first addend of which is connected to the output of the first adder modulo 2, and the input of the second addend to the input of the element NOT, the output of the block and the output of the register, whose information input is connected to the output of the multiplexer, the control input of which a block whose write enable input is connected to the register write input. 1 40 o # oa: J7 J4 35 42 o- FIG. 2 .J5 P Jtf one 53 Fi.Z FIG L FIG. five $ ig. 6