SU1723658A2 - Device for clock synchronization and separation of pulse burst - Google Patents

Abstract

The invention relates to a pulse technique and can be used for number-pulse information coding. The purpose of the invention is to expand the functionality by additionally forming adjustable bursts of pulses in a predetermined interval of an asynchronous signal with simultaneous formation of a pulse of adjustable duration - achieved by introducing a JK flip-flop 9 with a delayed response, the third and fourth elements AND-HE 10, 11, element 12, bus 12 3 mode selections, third and fourth output buses T5 and 16. The device also includes a synchronization bus 1, an input bus 2, a control bus 3, an inverter 4, two D-flip-flops 5, 6, first, second The elements AND-NOT 7, 8. 2 Il.

Description

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with

The invention relates to a pulse technique, in particular, to a generator that temporarily assigns an asynchronous signal at a clock frequency and, in addition, generates adjustable pulse series in the interval of the asynchronous signal, and can be used for number-pulse coding information.

A pulse train shaper is known that contains two flip-flops. A disadvantage of this device is that it does not have an output on which the first synchronized pulse of each transmitted pulse train is formed.

A clock synchronization device is known, which contains two triggers and a matching element, one input of which

connected to the sync bus and to the C input of the first trigger, two other inputs are connected to the forward outputs of the first and second trigger, and the output is connected to the output of the bus and the C input of the second trigger, whose S input is connected to the forward the output of the first D-flip-flop, whose D-input is connected to the R-input and to the output bus, and the inverse output is connected to the D-input of the second flip-flop

A disadvantage of the known clock synchronization device is that it cannot form bursts of pulses at the output.

Closest to the proposed technical essence and circuit design is a device for clock synchronization and selection of a burst of pulses, containing VI

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input input, two triggers, two IS-NOT elements and an inverter, whose input is connected to the sync bus and the first inputs of the first and second IS-NOT elements, whose outputs are connected to the first and second output buses, respectively, the output of the inverter is connected to the counting input the first D-flip-flop, the direct and inverse outputs of which are respectively connected to the installation and information inputs of the second D-flip-flop, the counting input of which is connected to the output of the second NAND element, the second input of which is connected to the second input of the first element ENTA, whose second input is connected to the second input of the first NAND element and the direct output of the first D-flip-flop, the third input is connected to the direct output of the D-flip-flop, and the information input of the first D-flip-flop is connected to the input bus.

A disadvantage of the known device of clock synchronization and pulse burst selection is the inability to regulate the number of pulses in a burst and form groups of pulses in the interval of the asynchronous signal duration, which significantly reduces its functionality

The aim of the present invention is to expand the functionality of the device by additionally forming adjustable pulse bursts in a predetermined interval of an asynchronous signal with simultaneous formation of a pulse of adjustable duration.

The goal is achieved by the fact that the device has a clock synchronization and a burst selection according to avt.ev, No. 884106, containing a synchronization bus, an input bus, two D-flip-flops, two IS-NOT elements and an inverter whose input is connected to the synchronization bus and the first the inputs of the first and second elements NAND, whose outputs are connected to the first and second output buses, respectively, the inverter output is connected to the counting input of the first D-flip-flop, the direct and inverse outputs of which are respectively connected to the installation and information inputs The signals of the second D-flip-flop, the counting input of which is connected to the output of the second element AND-NOT, the second input of which is connected to the second input of the first NAND element and the direct output of the first D-flip-flop, the third input connected to the direct output of the second D-trigger , JK-trigger with delayed response, the third and fourth elements AND-NOT, the AND element, the mode selection bus, the third and fourth.

bus, and the D-input of the first trigger is connected to the input bus and the first input of the third element AND-NOT through the element And, the second input of which is connected to the output

the fourth NAND element, the first input of which is connected to the mode selection bus, the second input — to the forward output of the JK trigger with a trigger delay; the J input of which is connected to the forward output of the first

0 trigger and with the third output bus, K- input - with the inverse output of the first trigger and with the second input of the third NAND element, the output of which is connected to the fourth output bus, the third input - with the bus

5 clock pulses.

At the same time, the JK-trigger with a trigger delay contains an RS-trigger, the first and second adjustable integrated RC circuits, each of which consists of a series-connected adjustable resistor and a capacitor, the second plate connected to the common bus, the first and second elements AND-NOT whose first inputs are inputs J and K, respectively, and

5 outputs through the first and second integrating circuits respectively are connected to the set and zeroing inputs of the RS flip-flop, the direct and inverse outputs of which are connected to the second inputs

0 of the second and first elements of the NAND, respectively, the direct input of the RS flip-flop is the forward output of the JK flip-flop with a trigger delay.

Since in this device, as compared with the known technical solution (in particular, with the prototype) there are new features, the proposal meets the novelty criterion.

Introduced JK-trigger with a delay of arrest, element of coincidence and elements of NAND are known from digital technology and applied according to their purpose. However, their connection with each other and with the rest of the device’s elements allows a significant

5 to expand the functionality of the device.

The clock synchronization and pulse burst extraction, adopted as a prototype, allows forming a synchronized pulse and a burst of pulses corresponding to the duration of the asynchronous signal, and the proposed device allows generating a synchronized pulse, an adjustable burst of pulses in a given

5 interval of the duration of the asynchronous signal, to form an adjustable burst of pulses in the interval of the duration of the asynchronous signal with the simultaneous formation of a synchronized pulse corresponding to the beginning of each

bursts of pulses, and on the third output bus, the device allows pulses of adjustable duration to be generated on the leading edge of the asynchronous signal, and on the fourth output bus to receive a batch of pulses spaced from the leading edge of the asynchronous signal for n + 1 pulses.

At the time of submission of the application materials, the authors are not aware of the claimed device for clock synchronization and separation of a burst of pulses, ensuring the achievement of the goal. Therefore, the proposal can be considered as satisfying the criterion. Significant differences.

A diagram of the device for clock synchronization and pulse burst allocation is shown in FIG. one; in fig. 2 given the diagram of the device.

The device for clock synchronization and pulse bursts contains synchronization bus 1, input bus 2, mode selection bus 3, inverter 4, two D-flip-flops 5, 6, elements AND-NE 7, 8 JK-trigger 9, elements AND-NOT 10, 11, match item 12, output buses 13-16.

J K-flip-flop 9 with a delayed response contains the first 17 and second 18 I-NOT elements, the first 19 and the second 20 integrating RC circuits, each of which consists of a series-connected adjustable resistor and capacitor, a second plate connected to a common busbar, and RS -Tpnrrep21.

The input bus 2 is connected to the first inputs of the match element 12 and the element AND-NOT 10, the second input of which is connected to the synchronization bus 1, the input of the inverter 4 and the first inputs of the elements AND-HE 7 and 8, the inputs of which are connected to the first 13 and second 14 output tires, respectively, the output of the inverter 4 is connected to the counting input of the D-flip-flop 5, the direct and inverse outputs of which are respectively connected to the setup and information inputs of the D-flip-flop 6, the counting input of which is connected to the output of the AND-HE element 8, the second input connected to the second in one of the NE-7 element, the direct output of the D-flip-flop 5 and the third output bus 15, the third input is connected to the direct output of the D-flip-flop 6, the installation and information inputs of which are connected through the first inputs of the AND-NOT elements 17, 18 (J and K inputs JK-flip-flop 9), adjustable resistances of the first 19 and second 20 integrating RC circuits with installation and zeroing inputs of the RS flip-flop 21, respectively, the forward and inverse outputs of which are respectively connected to

the second inputs of the elements AND-NOT 18, 19. The first input of the element AND-NOT 11 is connected to the control bus 3, the second input is connected to the direct output of the RS flip-flop 21, which

is the direct output of the JK-flip-flop, and the output with the second input of the coincidence element 12, the output of which is connected to the information input of the D-flip-flop 5, the fourth output bus 16 is connected to the output

0 element AND-NOT 10, the third input of which is connected to the inverse output of the D-flip-flop 5. The device operates in two modes. 1st rez and m. The formation of a burst of pulses in the interval of the duration of an asin5 chronical signal and the formation of a synchronized pulse corresponding to the beginning of the burst.

A low level is applied to the control bus 3, which overlaps the element E0 NOT 11, thereby eliminating the influence of the delays generated on the JK trigger 9 with a response delay, t, e. on elements

17.18, integrating the x 19, 20 and RS-trigger circuit 21. The device is working

5 is similar to the device, taken as a prototype.

2nd mode. The formation of adjustable bursts of pulses in the range of the asynchronous signal

0 the formation of synchronized pulses corresponding to the beginning of each pack of pulses. The formation of a pulse on the leading edge of the asynchronous signal. A high level is applied to the control bus 3, which allows 11 delayed pulses through the NAND element to be generated on the JK trigger 9 with a response delay, i.e. elements 17,

18, RC circuits x 19, 20, and RS flip-flop 21, which are fed to a matching circuit 12.

In the initial state on the input bus 2 the low level, the clock pulses arrive on the synchronization bus 1 (Fig. 2, a), the output of the inverter 4 is inverse

5 clock, trigger 5 in zero state. The low level of the direct output blocks the NAND elements 7, 8 and sets the trigger 6 on the installation input to the unit state, on the output buses 13, 14

0 (Fig. 2, e, g) - high levels, trigger 21 - to one state, on the third output bus 15 - low level, and on the fourth 16 - one (Fig. 2, p). Trigger 5 is in suspend mode. The input asyn5 chronic pulse (Fig. 2, b) sets a high level at the D input of the trigger 5 when the level goes from low to high at the output of the inverter 4, therefore, a single state is set at the C input of the trigger 5 (Fig. 2 ). High level

direct output of the trigger 5 permits the passage of clock pulses from bus 1 through the IS-NOT 7 element to the output bus 13 (Fig. 2, e), one pulse passes through the IS-HE 8 element to the output bus 14 (Fig. 2, f ). At the end of the output pulse on the output bus 14, a difference is generated from a low level to a high one, according to which trigger 6 (at its D input low level of the inverse output of trigger 5) is set to the zero state (Fig. 2, h) and low forward level the output overlaps the element IS-HE 8. Also, the high level of the direct output of the trigger 5 sets a low level (Fig. 2, I) at the output of the element IS-HE 17, since its second input has a high level (Fig. 2, o) coming from the inverse trigger output 21. When set to a low level on the output E of the NE-NE element 17, the capacitor of the integrating circuit 19 is discharged (Fig. 2, l) to the actuation level at the input of the RS flip-flop 21, while at its direct output (Fig. 2, n) a high level is set, which is at the output element AND-NOT 17 sets high, and at D-input of trigger 5 (FIG. 2, e), through element AND-NE 11 and the matching element 12 sets low, and trigger 5 returns to the zero state if there is a C input. differential from low to high, coming from the output of the inverter 4. A low level of the single output of the trigger 5 sets to S - the trigger 6 is entered into the unit state and the AND-NE elements 7 and 8 are reset, and a high level from the inverse output sets a low level at the output of the AND-HE element 18 (FIG. 2, k) and allows the passage of pulses of the clock frequency from bus 1 through the element AND-NOT 10 (FIG. 2, p) to the output bus 16. When a low level is set at the output of the element AND-NOT 16, the capacitor of the integrating circuit 20 is discharged (FIG. 2, m) to the actuation level at the input R of the flip-flop 21, while at its forward output a low level sets the output of the fourth element AND-HE 18 to a high level and at the 0-exit (Fig. 2 d) trigger 5 through the element IS-NE 11 and the match element 12 sets a high level and the process is repeated until it is set to input Noah bus 2 low. At the end of the input asynchronous signal, the device returns to its original state. By changing the resistance of the adjustable resistor of the integrating circuit 19, the delay n and the triggering of the flip-flop 21 at the input S, which corresponds to the duration of the high level at the direct output of the flip-flop 5, and

consequently, the duration of a burst on the output bus 13. By varying the resistance of the adjustable resistor of the integrating circuit 20, the delay T2 of triggering 21 at input R changes to a low level at the forward output of trigger 5, respectively, and the interval between pulse bursts on the output bus 13 or the duration of a burst of pulses (Fig. 2, p) on the output bus 16, the initial impulse of which is separated from the front of the asynchronous signal coming from the input bus 2 for the duration of the high interval level

at the direct output of the trigger 5 (Fig. 2, d). During formations on the output bus 13 of a single burst of pulses on the output bus 15, a pulse is formed along the leading edge of the asynchronous signal, on the output bus

16, a burst of pulses is formed, separated from the leading edge of the asynchronous signal by an interval corresponding to the duration of the burst of pulses on the bus 13. The layout of the claimed device was assembled and tested under laboratory conditions. In the device, 155 series chips were used. Variable resistors integrating circuits 470 ohms. In the first integrator circuit 19 was used

a 0.47 microfarad capacitor and a second capacitor 20 1 microfarad. At the same time, the delay time Γ | introduced by the integrating circuit 19 is adjustable from 10 to 300 µs, and the delay time T2 introduced by the integrating circuit 20, from

10 to 450 µs.

1st mode. The control bus 3 is supplied at a low level, then the device operates in the same way as the device, taken as a prototype.

2nd rez and m. Control bus 3 is fed high. On the synchronization bus 1, pulses with a repetition frequency of 1 MHz were applied, and on the input bus 2 - asynchronous signals with a duration of 0.5 ms

and a repetition rate of 1 kHz. The following signals were formed on the output tires. When TI was set to 20 μs, yy 30 μs, on the output bus 19 in the interval of the asynchronous signal 0.5 ms, ten bursts of pulses of 20 pulses were formed in a packet with an interval between bursts of 30 μs. On the output bus 14 in the interval of the asynchronous signal, a packet of 10 pulses was formed, corresponding to the beginning of each packet.

on the output bus 13. The pulse duration corresponded to the duration of the sync pulse, and the repetition period was 50 μs. On the output bus 15 in the inter-room asynchronous signal was formed

a pack of 10 pulses. The pulse duration is 20 µs and the repetition period is 50 µs. On the output bus 16, in the interval of the asynchronous signal, 10 bursts of pulses of 30 pulses per burst and a repetition period of 50 µs were formed. In this case, the first packet is removed from the leading edge of the asynchronous signal for 20 µs or 20 sync pulses.

When ri was set to 200 μs, ng ZOO.ms on the output bus 13 in the 0.5 ms asynchronous signal interval, one burst of 200 pulses was formed, on the output bus 14, one pulse was generated from the leading edge of the asynchronous signal to the beginning of the packet on the output bus. On bus 15, a single pulse was formed from the leading edge of an asynchronous signal with a duration of 200 µs. On the output bus 16, a burst of 300 pulses was formed, which was 200 µs or 200 clock sync pulses away from the leading edge of the asynchronous signal.

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Claims (2)

1. A device for clock synchronization and separation of a burst of impulses according to auth.St. No. 884106, which is based on the fact that, in order to extend the functionality by additionally generating adjustable pulse bursts in a predetermined interval of an asynchronous signal with simultaneous generation of a pulse of adjustable duration, a JK trigger with a delay is introduced into it, .i tiy and fourth elements AND-NOT, element And, the bus mode selection, the third and fourth output tires, and the D-input of the first trigger is connected to the input bus and the first input of the third NAND element through an AND element, the second input of which is connected to the output of the fourth NAND element, the first input of which is connected to the mode selection bus, the second input to the direct the output of the JK flip-flop with a trigger delay, the J-input of which is connected to the direct output of the first trigger and to the third output bus, the K-input with the inverse output of the first trigger and to the second input The third element is NAND, the output of which is connected to the fourth output bus, the third input is connected to the clock pulse bus. 2. The device according to claim 1, wherein the J K-trigger with a delayed response contains an RS-trigger, the first and second adjustable integrating RC circuits, each of which consists of sequentially connected adjustable resistor and capacitor, the second lining connected to the common bus, the first and second elements of AND-NOT, the first inputs of which are inputs J and K, respectively, and the outputs through the first and second integrating RC circuits, respectively, connected to the installation and outgoing inputs RS flip-flop, direct and inverse outputs otorrhea connected to second inputs of first and second AND-NO elements, respectively, a direct output of RS-trigger is a direct output of JK-flip-flop with the delayed actuation.