SU1714609A1 - Device for shaping main memory unit test - Google Patents

Abstract

The invention relates to computing and can be used to control RAM. The purpose of the invention is to increase the reliability of the control by increasing the number of searches of address chains when reading. The device contains triggers 1, 2. counters 3, 4. element OR is NOT 5, counter 6 modulo K, summation block 7, switch] 8, registers 9, 10. element OR 11. a group of hacks NOT 12. element I 13, multiplexer 14, direct and inverse synchronization inputs 15, 16 controlled by the RAM 17. Information is read from the addresses not consecutively, sequential search is performed for only half of the addresses, after each address information is read from the address obtained by inverting all bits of this address. Changing the order exacerbates the interference, and the inversion of all bits of each address places the address selection circuit under the most severe conditions. 5 il.

Description

J

ABOUT

oh oh

The invention relates to computing and can be used to control random access memory devices.

The aim of the invention is to increase the reliability of the control by increasing the number of searches of address chains when reading.

FIG. 1 shows a diagram of an apparatus for generating a test of a RAM block; figure 2 is a diagram of the modulo K; FIG. 3 is a diagram of the summation block; figure 4 - diagram of the switch; Fig. 5 is a time chart of the formation of the read address.

The device contains the first 1 and second 2 triggers, the first 3 and second 4 counters, the element OR NOT 5, the counter 6 modulo K, the blocking of the summation, the switch, the first 9 and second 10 registers, the element ILI 11, the group of elements NOT 12, the element AND 13, multiplexer 14, direct synchronization input 15 of the device, inverse synchronization input 16 of the device, and memory block 17 ..

Counter b modulo K (FIG. 2) contains a counter 18, a comparison block 19, an AND element 20 and a trigger 21,

The summation unit 7 (FIG. 3) contains a register 22, an adder 23. The first group of elements is AND 24, the second group of elements is And 25, a group of elements is OR 26. The register is 27, the element is NOT 28.1K-trigger 29 and the element is AND 30.

Switch 8 contains the first 31 and second 32 groups of elements AND, a group of 33 elements OR, and a trigger 34.

The device works as follows.

Triggers 1 and 2, counters 3 and 4, block 7 and switch 8 are set to state O. Register 10 contains the number K - the number of groups. The output of block 7 is set to zero address. The outputs of the counter 4 and the element OR-IE B are set to zeros. Triggers 1 and 2. Counters 3. 4 and 6 on signal 1 on the counting input, as well as block 7 and on-switch 8, are switched by the decay of this signal.

In the first cycle of operation, the read and write O is performed over the entire array of the memory block 17.

Under the influence of signals from inputs 15 and 16, bpok 7 goes through all the addresses in memory block 17, the first address of which is zero. At the end of the pth clock cycle, according to the transfer signal of block 7, counter 4 switches, trigger 1 also switches to state 1. allowing the starting address of co-counter 6 to be entered into block 7, opening element 13 and setting read.

block 17. The operation of block 7 is prohibited, the operation of the first and second channels of the multiplexer 14 is allowed. The next 2n clock cycles of address searches are performed by a counter 3. which iterates sequentially, and the information from the inverse address is read to each selected address. Switching of addresses triggers 2 according to the signal coming through the element 13 to the control input of the multiplexer 14.

The second cycle: get all the code combinations for each address group and read according to the specified algorithm after writing each code combination. At the same time, the code combination 0 ... 01, coming from counter 4, is recorded in the group of addresses that the summation block 7 generates.

Upon the decay of the transfer signal from the summation block 7, the counter 4 switches to the next state 0 ... 010, the trigger 1 switches to the state 1, from the inverse output of the trigger 1 to the second control input of the multiplexer 14 the signal O comes, and from the direct output trigger 1 to the second input element And 13 - signal 1.

In subsequent cycles, the initial address of the group is entered from the counter.

6 according to the module K in block 7, the summation and reading of information at all addresses in order of increasing, but with the inverse of each address. Then, a new code combination 0 ... 010 is written to the same address group, and after recording is completed, trigger 1 switches back to state 1, and Read information according to the specified algorithm is set again.

After writing the code combination 11 ... 11, the counter 4 switches to the 0 ... 00 state and appears at the output of the OR-NOT 5 element 1. After writing the code combination 0 ... 00, the counter 4 switches to the 0 state. ..01 and at the output of the element ILINE 5 is set to O. On the falling edge of signal 1, the unit OR of NO 5 adds one to counter 6 modulo K, and when reading information into the block

The 7 summarizes the starting address of the next group.

Similarly, all codewords are recorded in other groups and information on the indicated algorithm is read after each codeword is recorded.

The output value of counter 6 modulo K is all the time compared with the value of K supplied to the information inputs of counter 6 of register 10. When the value at output of counter 6 modulo K becomes equal to K and 1 appears in the highest bit

the counter 3, the counter b is reset with signals from the inverse of the synchronization input 16. Thereafter, the summation of the signals from the input 15 is entered into the starting address of the first group, and the second cycle is repeated.

Counter b modulo K (figure 2) works as follows.

The start of operation is set to the state O of the counter 18. At the same time, the output of the comparator unit 19 and the element 20 sets the signal O, and the inverse output of the trigger 21 the signal 1. By dropping the signal 1 coming to the counter input of the counter 18, its contents increase by one. When the contents of counter 18 become equal to the number K supplied to the second inputs of comparator unit 19, signal 1 is set at the output of the signal 1, which arrives at the second input of element AND 20. After the first input of element AND 20 of signal 1 appears at the trailing edge of the single signal, the trigger 21, it switches to state 1 and on its inverse output sets the signal O, which resets the counter 18.

The summation unit 7 (FIG. 3) works as follows.

Before starting, the registers 22 and 27 are reset, the control input of the summation unit 7 is given a signal O, the summation control input of the summation unit 7 is a signal 1. Thus, the outputs of the adder 23 through the second group of elements AND 25, the group of elements OR 26 are connected to register 27 in which the zero address is located. By the decay of the inverted inversion signal, which enters the control input, parallel recording of information in the register 22, information from the register 27 is entered into the register 22. The contents of the register 22 and information from the output of the switch 8 are added to the adder 23, and by the decay of the inversion signal arriving at the input control the parallel entry of information, the sum is entered in the register 27. If there is no transfer signal when adding in the adder 23, then the signal 1 is set by decreasing the signal of inversion on the inverse output of the trigger 29 steps to the second input of the AND 30 to the first input of which is supplied the input signal from the control unit 7 summing summing. At the same time, the signal G. is set at the output of the transfer of block 7

If the transfer signal appears in addition to the adder 23, then the trigger 29 is set to state 1 by decreasing the inversion signal and the O signal is set at its inverse output. By dropping the signal from the inverted output of trigger 29 it switches to state 1 trigger 1. At that the input of the entry control of the summation block 7 is set to 1, and the input of the summation control of the summation block 7 is O. Thus, the outputs of the counter 6 are connected modulo K through the first group of elements AND 24 and the group or. 26. The initial value supplied to the information inputs of the first group of the summation unit 7 is entered into the register 27 by the decrease in the signal to go to the register 27. The signal O from the control input of the summation of the summation block 7 blocks the element AND 30, and a signal O appears at the transfer output of the summation block 7.

Switch 8 (figure 4) works as follows

Before the start of operation, the trigger 34 is set to the state O, and its inverse output is set to 1, and the information coming to its first inputs passes at the output of the switch 8. When a single signal arrives at the control input of the switch 8, the trigger 34 switches to state 1, O is set to its inverse output, and the information received at the second inputs of the switch 8 passes to its output. The elements NOT 12 allow you to change the algorithm for selecting the address when reading. After each selected address, the information from the address obtained by inverting all bits of this data is read. Inversion of all bits of each address puts the address selection circuits in the most severe conditions, since various interferences, interferences, failures are related to the number of circuits in which switching occurs at the same time, therefore with the appearance of another addressing source (elements 12) The availability of control is based on the increase in the number of switches of the address circuits of the tested RAM in a unit of time when read in comparison with other group tests considered in the known device.

Counting trigger 2 affects the change in the formation of the dough as follows. The signal from the counting trigger 2 through the element And 13 is fed to the first control input of the multiplexer 14. When switching the trigger 2, the first and second channels of the multiplexer 14 are switched, i.e. the checked RAM from the multiplexer 14 receives the forward address (from counter 3) or the inverse address (from the elements NOT 12).

Thus, the signal from the counting trigger 2 switches addresses (direct or inverse) to the readable RAM.

By the decay of a single signal from trigger 2, counter 3 switches, i.e. the address stored in the counter 3 is incremented by one.

The register 9 (10) is incremented by the address, when summed with the previous address stored in the summation block 7, the real address is formed, at which information is recorded into the checked RAM, the register 9 increments the address needed to obtain the addresses in the first device operation cycle. Since the addresses in the first cycle are iterated sequentially, one is stored in register .9.

The register 10 registers the increment of health needed to obtain the addresses in the second cycle when writing to the address group is in progress, so the number K (number of groups) is entered in register 10. Each group includes addresses that are equal in absolute value to K.

In module 6 modulo K, the initial address of the group is stored, i.e. the starting address to which you need to add the numbers K, 2K, 3K and so on to get the addresses of this group. First, in the counter b modulo K is O. After recording all the code combinations at the addresses of one group, the contents of counter b modulo K increase. is per unit.

When the value at the output of counter 6 modulo K becomes equal to K and 1 appears, in the high bit of counter 3, counter 6 is reset. T, e. in counter 6 to

the module, K holds the value O, 1, 2 K-1,

0,1,2К-1, etc.

Claims (1)

Claims — A device for generating a test of a random-access memory block containing a first counter, the highest bit output of which is connected to the counter input modulo K (where K is the number of test case groups), with the control input of the switch and with the first input of the OR element, the output of which is connected to the counting input of the first trigger, whose direct output is the output of the device for connecting to the read control input of the tested memory block, the inverse output of the first trigger is the output of the device for connecting to the recording control input of the unit under test memory, the second counter, the bit outputs of which are connected to the group of inputs of the element OR NOT and are the outputs of the device for connection to information inputs of the tested memory, the input element OR is NOT connected to the output of the switch, the first and second groups of information inputs of which are connected to the outputs of the first and the second register, the switch output group is connected to the information inputs of the first group of the summation unit, the modulo K counter, whose information inputs are connected to the outputs of the second the register, the synchronized input of the modulo K counter is the inverse synchronization input of the device and is connected to the inverse synchronous input of the summation block, the counting input of the modulo-K counter is connected to the output of the OR-NOT element, and the bit outputs of the modulo-K counter to the information inputs of the second group the summation unit, the direct synchronization input of which is the direct synchronization input of the device, the entrancing and summing control inputs of the summation unit are connected respectively to the direct and inverse outputs of the first trigger, you the transfer of the summation block is connected to the counting input of the second counter and the first input of the OR element, characterized in that, in order to increase the reliability of the control by increasing the number of searches circuits when reading, the element Y is entered into the yqt, the second trigger, the multiplexer, the group of elements is NOT, the counting input of the second trigger is connected to the forward synchronization input of the device, direct the output of the second trigger - with the first input of the element I and the counting input of the first counter, the bit outputs of which are connected to the inputs of the elements NOT the group and the first information inputs of the multiplex; the outputs of the elements NOT the group with the second information inputs of the multiplexer; the outputs of the summation block are connected to the third information inputs multiplexer, outputs which are address outputs of the device for connection to the address inputs of the memory block under test, the direct output of the first trigger is connected to the second input of the AND element, the output of which is connected to the first control input of the multiplexer, the second control input of which is connected to the inverse output of the first trigger . . 4 J j  M " 1 "about 5 V) "| | H