SU1711194A1 - Tv image amplitude histogram evaluator - Google Patents

Abstract

The invention relates to computing and can be applied in digital image processing systems. The purpose of the invention is to enhance the functionality by accumulating histograms for various image fragments. Fragment addresses are formed by the fragment selection block for the current sweep coordinates at the output of the block of counters of the number of elements and lines. The addresses of the fragments in the memory block accumulate the corresponding histograms. 1 il.

Description

The invention relates to computing and can be applied in digital image processing systems.

The purpose of the invention is to enhance the functionality by accumulating histograms for various image fragments.

The drawing shows a diagram of the device.

The device contains a clock pulse generator 1, a block of 2 counters of the number of elements and lines, a synchronization block 3, an analog-digital converter A / D converter 4, a block for extracting image fragments, including the first 5 and second 6 comparison circuits, the first 7 and second 8 registers, and the multiplexer 9 coordinates , data multiplexer 10, address multiplexer 11, write / read multiplexer 12, memory unit 13, unit adder 14, input / output unit 15, trunk 16.

The device works as follows.

The block 2 of the counters of the number of elements and lines 2, clocked by the generator 1, forms a set of control signals for the block 3 of synchronization, as well as for the external television sensor. The image video signal received by this sensor is fed to the input of the A / D converter 4, which, using generator 1, samples the video signal in time and quantizes it in amplitude. The digitized ADCs 4 luminance values of each image element of the television lines are fed to the first input of the address multiplexer 11. Using the multiplexer 11, the addressing source of cells within individual memory areas of block 13 is selected. At the same time, the address source of the areas themselves is selected by 9 coordinate multiplexer. Each address value at the output of multiplexer 9 corresponds to specific fragments of the image for which amplitude histograms are calculated. Second information entry

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The multiplexer 9 coordinates is the high-order bits of the counter of the number of elements and the counter of the number of rows, the values of which are fixed in the first 7 and second 8 registers and allow to obtain a large-scale coordinate grid in the plane of the television frame. The boundaries of the grid define fragments of images in which histograms are calculated.

Before starting the computations, all the multiplexers 9-12 are transferred to receive information from the I / O unit 15. This translation is carried out by signals from the outputs of block 15 to the control inputs of the multiplexers. Next, the entire memory of block 13 is reset by sequentially iterating through the addresses of all its cells through multiplexers 9 and 11 with zero input data and simultaneously sending a recording signal through multiplexer 12. Signals controlling zero reset of memory 13 are generated by block 15, which is controlled by an external system (computer or microprocessor) through line 16 and contains the input / output ports of the external system. Upon completion of zeroing the memory block 13, the multiplexers 9-12 along the control inputs are switched to the mode of receiving information from the internal channels of the device.

The amplitude histogram calculation starts from the trigger signal, which is fed to the trigger input of the synchronization unit 3. The trigger signal is generated at the initiative of the external system by programmatically setting the logic 1 state to a certain bit of the I / O port in block 15. Under the control of the trigger signal, the synchronization block 3 generates the call control signals to the memory block 13, which are received through the multiplexer 12 reading during forward moves of lines of the entire frame of the image, starting from the first line. The control signals for accessing the memory unit 13 provide for its selection, setting the read and write mode for each sample of the input image. Each successive call to memory block 13 is divided into two clocks. In the first cycle, the contents of the memory cell are read and the contents are increased by one using the adder 14. In the second cycle, the obtained result is written through the multiplexer 10 into the memory block 13. The address of the memory cell for each reference is determined by the amplitude value at the output of the A / D converter 4 and the number of the fragment of the image in which the histograms are being counted.

The fragment number is fixed in the first 7 and second 8 registers and represents the highest bits of the counter of the number of elements in a row and the counter of the number of rows (a large-scale coordinate grid in the plane of the television frame). Said counters are located in block 2,

0, the second and third outputs of which are the low and high bits of the item counter, respectively, and the fourth and fifth low and high bits of the row counter. The low order bits are used to determine the moment of crossing the boundaries of the fragments. This moment of time is determined by comparison circuits 5 and 6 and is accompanied by pulses at their outputs, which record the values of the higher bits of the element and row counters in registers 7 and 8. Values with which the lower bits of the element and row counters are compared (the size of the large-scale grid ) are set by the external system. / Install any possible

5 values allows displacing a large-scale grid defining the boundaries of the fragments of the image plane with the accuracy of the size of the discrete reference. Source offset values for the external system

0 can serve as an interactive tool or automatic pointer (light pen, cursor, etc.).

Claims (1)

Apparatus of the Invention A device for computing amplitude histograms of television images, comprising a clock pulse generator, the output of which is connected to clock inputs of an analog-digital converter, a synchronization unit and a block 0 counters of the number of elements and rows, the first output of which is connected to the synchronization input of the synchronization unit, the startup input of which is the computing start input of the device, the input of the initial data setup of which is connected to the first information input of the data multiplexer, the output of which is connected to the data input of the block a memory whose output is connected to the information accumulator of the unit adder, 0 the output of which is connected to the second information input of the data multiplexer, the control inputs of the data multiplexers, addresses and write-reads are connected to the input of the initial installation settings5 calculation of the device, the write-read control input of which is connected to the first information input of the read-write multiplexer whose output connected to the control input of the read / write memory block, the first whose address input is connected to the output of the address multiplexer, the first and second information inputs of which are connected to the first input of the device address and the output of the analog-digital converter, respectively, whose information input is the information input of the image elements of the device, the second output of the block of the number of elements and lines is connected with an information input of an image extraction unit, characterized in that, in order to extend the functionality by 0 accumulating histograms for different image fragments, the output of the synchronization block is connected to the second information input of the read-write multiplexer, the second input of the address of the memory block is connected to the output of the fragment selection block, the inputs of the initial setup-calculation modes, the fragment address and the fragment parameters are the input of the setting of the initial installation-calculation modes, the second input of the address and the input of the setting of the parameters of the device fragments, respectively.