SU1700760A1 - Unit for transmitting signals of multiple frequency - Google Patents

Abstract

The invention relates to power, communication. The purpose of the invention is to improve the noise immunity. The device for transmitting multi-frequency signals comprises a code sequence generation unit t, a generator of 2 clock pulses, a control unit 4, a first frequency grid generator 6. With the introduction of the phase shifter 3, blocks 5.7, generation of the frequency control code, the second generator B of the frequency grid, quadrs 9 and 10, multipliers 11 and 12, synchronization unit 13, adder 14, low-pass filter 15, spectrum converter 16 of the radio transmitter 17 masking ability of the device, which leads to increased noise immunity. 6 Il.

Description

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The invention relates to telecommunications, in particular to the transmission of information over communication channels with interference.

The purpose of the invention is to improve the noise immunity.

Fig. 1 shows a structural electrical circuit of the device proposed; figure 2 - diagram of the spectrum converter; FIG. 3 is a diagram of a frequency grid generator; Fig. 4 is a block diagram diagram of the formation of code sequences; Fig. 3 is a block diagram of the formation of the frequency control code; 6 is a control block diagram.

The device contains a block 1 of the formation of code sequences, a generator of 2 clock pulses, a phase shifter 3, a block of 4 controls, the first block 5 of the generation of the frequency control code, the first generator of the frequency grid, the second block 7 of the formation of the code of frequency control, the second generator 8 of the frequency grid, squares 9 and 10, multipliers 11 and 12, a synchronization unit 13, an adder 14, a low-pass filter 15, a spectrum converter 16, a radio transmitting device 17.

Transducer 16 comprises amplifier 18, spectrum analyzer 19, control signal generator 20, tunable filter 21, power amplifier 22. The frequency grid generators contain a differentiating circuit 23, a pulse shaper 24, capacitors 25 and 26, transistors 27 and 28, comparators 29 and 30, differentiating circuits 31 and 32, pulse shapers 33 and 34, triggers 35 and 36, voltage dividers 37 and 38 .

Block 1 contains analog-digital converter 39, buffer registers 40-43, counter 44, demultiplexer 45, triggers 46 and 47, multiplexers 48 and 49, counter 50, matching blocks 51-56, multiplexers 57 and 58.

Blocks 5 and 7 contain buffer register 59, analog-to-digital converters 60 and 61, block 62 matches, counter 63, demultiplexers 64 and 65, buffer register 66, inverters 67 and 68.

The control unit 4 comprises a random number generator 69, a shift register 70, a shift register 71, an OR element 72, an AND element 73-75, a generator 76-78, dividers 79 and 80, a shaper 81

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pulses, inverter 82, driver 83 sync pulses, adder 84, storage unit 85.

The device works as follows.

The signal from the source is fed to the input of the code sequence generation unit 1, where the signal is encoded and a burst is generated. Next, the N parallel channels receive signals to the N inputs of multipliers 11 and 12. The control unit 4 calculates, according to a predetermined algorithm, the frequencies of the signal components and, therefore, the frequency of the generator 2 clock pulses and the division factors of the dividers of the generators 6 and 8. The signal from the generator 2 comes to the frequency grid generator 6 and through the phase shifter 3, which changes the signal phase by 90 °, to the frequency grid generator 8. The dividers division factors calculated by the control unit 4 can be varied and set using blocks 5 and 7, which convert serial digital signals into parallel ones, record them and convert them to analog control voltage. The signals from the output of the generator 6 through the quadrants 9 and 1C are fed to the inputs N of the multipliers 11 and 12, they are multiplied with the signals from the outputs of the generator 8 to the block 1. Next, the signals are summed in the adder 14,

using filter 15, the signal is converted from digital form to the set of harmonic components and through converter 16 enters the radio transmitter 17. The presence of an oscillator 8, block 7, quadrants 9 and 10, multipliers 11 and 12, phase rotation of bodies 3, adder 14 and converter 16 is due to the fact that the optimum energy spectrum of the multi-frequency impulse pulse bundle should be as follows:

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where & W is the frequency interval; 3t - frequency index; v - time index; Amia minimal pulse amplitude;

T - the duration of the time interval; & t is the distance between two times

variable elements; The law determines the choice

L SO; U03 - spacing between adjacent

frequencies;

S is the number of pulse bursts; n - the number of pulses in the pack. The information about changing the DSL intervals (or the law Y)) comes from block 4 through synchronization block 13 to the radio transmitter 17 and is transmitted to the recipient of the message via a separate narrowband channel. Converter 16 converts the spectrum of the generated multi-frequency signal according to the above algorithm: the signal is amplified, delivered to the analyzer) 19, the output of which with the help of shaper 20 generates a signal; changing the frequency response of the tunable filter 21 depending on the spectrum of the input signal, after which the signal goes to the amplifier 22.

The generator frequency grid works as follows.

The input pulse train with the help of a differentiating circuit 23 and the driver 24 is converted into a pulse train whose duration does not depend on the frequency of the input signal. Capacitors 25 and 26, transistors 27 and 28, comparators 29 and 30, differentiating gce circuits 31 and 32, formers 33 and 34, and triggers 35 and 36 form frequency converters. The division factor of each divider is determined by the voltage at the second input of the comparator and depends on the input control signal on the buses. The presence of voltage dividers 37 and 38 is due to the fact that the division factors differ by 2 hectares. The block 1 of the formation of code sequences, using an analog-digital converter 39 converts the analog signal into a digital form and records N values into N buffer registers 40 and 41 and the following K values

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into buffer registers 42 and 41. Counter 44, demultiplexer 45 and triggers 46 and 47 form write and read signals. Upon completion of writing to the first N buffer registers 40 and I, the parallel code is converted and converted into serial code using multiplexers 48 p 49 and forming the addresses of the counter 30 and blocks 51 - 56, which allows generating pulse packets with the required T0 and t values. . Then reads from registers 42 and 43. The second input of the device receives the clock frequency pulses from the control unit 4, and the third input receives a sequence of pulses with the required TQ and u.t.

The frequency control code generation unit (Fig. 5), using a multiplexer 65, writes into the buffer registers 66 and 59 N values of the division factors of the frequency grid generators, which are converted into control voltage by means of converters 60 and 61. the impulse p of recording the st of control unit 4 at the end of the calculation of the values of the division factors; another input of block 62 receives a sequence of pulses from the control unit 4, from which, using a counter 63, demultiplexer 64 and inverters 67 and 68 write and read signals for buffer registers 66 and 59 are generated. The control unit contains a generator 69, the output of which writes numbers to register 71, the output of which, after writing the Nth number, is an overflow signal controlling the operation of trigger 70 the beginning and end of the cycle for the generator 69. The signal of the beginning of the cycle by means of the generator 83 transponders and the adder 84 transmits the signal. Using the generator 77 of the element And 73 and the element I 72 is made into the record in the register 71. The signal at the end of the cycle with the help of the generator 76, the element AND 74 and the element OR 72 reads the data at the corresponding output. The generator 78 generates clock pulses, from which, using a divider 79, a driver 81, control signals are generated with given values of T0 n & t. 82 of them using an inverter,

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An element 80 and element 75 generates a signal that permits an hour control code to be written to the block. The permanent memory block 85 contains information about the value of the frequency., 1 clock generator.

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Claims (1)

An apparatus for transmitting multi-frequency signals comprising a code sequence generating unit, a control unit, a first frequency grid generator, a clock pulse generator, characterized in that, in order to improve the noise immunity, the first, second frequency control code forming unit, the second phaser, are introduced - | A raster of a frequency grid, N quadrants, | Ы multipliers, a series-connected adder, a low-pass filter, a spectrum converter, and a radio | transmitting device, and the synchronization unit "wherein the first input code sequence generating unit is input to the device, and the second and third inputs connected respectively to the first and eight 0 five 50 the second outputs of the control unit, the third and fourth outputs of which are connected respectively to the inputs of the synchronization unit and the clock pulse generator, the output of which is connected to the inputs of the phase shifter and the first frequency grid generator, the outputs of which are connected through quadrants to the first inputs of N multipliers, the outputs of which are connected to the inputs of the adder The fifth, sixth, seventh outputs of the control unit are connected to the corresponding inputs of the first and second frequency control code generation units, the outputs of which are connected They are connected to the corresponding inputs of the first and second frequency grid generators, respectively, the output of the phase shifter is connected to the control input of the second generator of the frequency grid, the outputs of which are connected to the second inputs of the multipliers, the third inputs of which are connected to the corresponding outputs of the generating unit, code sequences, output of the synchronization unit connected to the second input of the radio receiving device, the output of which is the output of the device. yu-M MZHM-Zh-lK Output FIG. 2 Output L Ym.3 Bxotl Fy F FI.5 LOST 8xad3 Output Bt / xoff