SU1698649A1 - Lump material digital level gauge for subterranean storages - Google Patents

Description

The invention relates to instrument making and can be used in a city building. rgicheskoy, hkchichskoy. and dsu. Il ogrstl 1 / promnennos t D 1 s-etomaticheskogo koptroo level lumpy i-a- terialeev, for example, the rock mass in underground reservoirs

 of the invention is an increase in the uncoupling ability of a Cc C-ri device (the study of measuring velm-i э e mutual with j, B, u3 fertile signals at the Gossin Vreg / En

Figure 1 shows the diagram. The vertical view shows the vertical capacity of the geoemal capacitance and the placement of the sensors (a), as well as the graph of the functional array of the USSR, the height of Z, the controlled photon, and the value of 6 shifts of the signal from the sensor relative to the signal Rley / kchego /. atchik b), from FIG. 2 is a diagram of the proposed device, GE-O and FIG. 3, an example of the distribution of impulses over discrete

1-ktch., Zaderhg1 / saddle of the PC Bcch / range signal, which is the height of the controlled gkk-enk n step in the f ar-yumm Ti d1 inter-f range of the co-division of the ef fs. the m-th value of the fiem level, with a discrete step equal to about in Fig. 4, is the 1st-Mutatol scheme and the memory unit.

The resolution of the device is due to the sequential measurement of the first signal input signal /, B at the times of the legs and the step of the O. time interval. KFrO-tero is equivalent to e1, and for the exact estimate of the height, 1 level.

Podzhe. on the capacitance., in which it accumulates, V, KOBJ. The material 2 is connected by layers -, with the help of mountainous excavation 3 from the section of the coastal zone and the harbor. and the lower section of the 5-with the production of h, where producing 3 - bif nazka material

(-.

OS

ABOUT

h

Claims (2)

one% from the tank. Sensors 5 and 6 are located in the mine work 4, the first of which is installed directly near the base of the tank, and the second one is distant from it. The sensors are connected mechanically via a teio-mountain massif with a capacitance of 1, and electrically connected to the measuring unit. In addition to sensors 5 and 6, the level control device includes drivers of 7 and 8 rectangular pulses connected by inputs with sensors 5 and 6, a generator of 9 clock pulses connected to the input of a coincidence element 10 connected by a second input to a driver 8, a shift register 11, associated with the information input with the output of the imaging unit 7, and the clock-input input with the output of the frequency divider 12 connected to the generator 9, the elements OR 13 connected with the groups of the bit outputs of the register 11, and the outputs through the keys 14 with the inputs of the elements OR 15 com Tator (multiplexer) 16 register outputs, connected by information inputs to first outputs of register 11 from each group, and output via key 17 to information input of shift register 18, connected by clock input to generator 9. And outputs through elements OR 15 - with inputs of elements 19 matches, pulse counters 20 connected by counting inputs to outputs of matching elements 19 connected by their second outputs to the output of matching element 10, overflow outputs of counters 20 are connected to information inputs of block 2 The processing and control unit 22 Bpok 22 / of the board contains a storage register 23 connected by information inputs together with the inputs of the OR element 24 to the information output of block 22, and output through the address output of block 22 to the address input of the switch 16 and a separate information input of the block 21, elements 25 and 26 of coincidence, connected by the first inputs through the synchronization input of block 22 with generator 9, with their inputs to the output of the element OR 27, the second input of the element of coincidence 26.cv is assigned to the output of the element OR 24, distributor 28 pulses (made, for example, in the form of an annular four-bit pulse counter), connected by the input to the output of the element OR 27, trigger 29, connected by an inverse output to the input of the matching element 30 and through the first control output of the block 22 to the control inputs of the keys 14, and non-inverted output - to the output of the coincidence element 31 and through the second output of block 22 to the control input of the key 17, a flip-flop 32 connected by the outputs via the matching elements 32 and 34 to the inputs of the flip-flop 29, while the zero output of the pulse distributor 28 is connected via the third output of the block 32 to the control inputs of the matching elements 19, the first output through the matching element 30 to the control input of the register 23 and the zero reset trigger 32, and through the matching element 31 0 to the trigger setup input 32 and through the fourth output of block 22 to the control input of block 21, the second output to the second inputs of matching elements 33 and 34, and the third output to the second input of matching element 25 and through the fifth output of block 22 to 20 counter reset inputs. The switch 16 consists of coincidence elements 35, the first inputs of which are connected via the information inputs of the switch 16 to the first outputs of the shift register 11 from each group, the second inputs through the address input of the switch 16 and the address output of the control unit 22 to the information output of the register 23, and 5 outputs through the element OR 36 and the switch 16 output to the key 17 input. The memory and processing unit 21 contains the first register 37 connected by information inputs through the first information input of the block 21 and the address output of the control unit 22 to the information output of the register 23, the second register 38 connected by information inputs through the second information input of block 21 to 5 outputs of counters 20, indicator 39, connected by information inputs to information outputs of registers 37 and 38, the control inputs of which are connected via the input of the unit 21 and the fourth 0, the output of block 22 with the output of coincidence element 31 (if necessary, block 21 may additionally contain other functional elements). The device works as follows. When material 2 is unloaded into underground tank 1, blows of its separate pieces and portions occur; the surface of the accumulated material at point A (FIG. a). These blows 0 cause seismic vibrations that propagate in the mountain range surrounding capacitance 1 and excite electrical signals in sensors 5 and 6, B 5 when sensor 5 is near the capacitor, signals appear earlier than the remote sensor 6. The magnitude of the shift (difference) signals in time, determined by the difference in the course of seismic rays through the body of the rock mass from point A to sensors 5 and 6, is functionally related to the height of the monitored level of material. The greater this height, the smaller the difference of the seismic rays and, accordingly, the shorter the time in the shift of the signal of the remote sensor 6 relative to the signal of the near sensor 5 (Fig. 16). The source of seismic vibrations at point A is common to both sensors, and therefore the signals arising in them are identical in structure. These signals can be distorted by interference, for example, from the impact of pieces of material against the walls of the container and from other sources. The useful signals and interference are not connected to each other, i.e. their amplitude and time ratios are random. At the same time, the useful signals from sensors 5 and 6 are physically interconnected with time in, which allows them to be distinguished from the interference with appropriate processing. The signals from sensors 5 and 6 are fed to the formers 7 and 8, where they are amplified and converted by means of a Schmitt trigger in a sequence of rectangular pulses with a constant amplitude corresponding to the level of a logical unit. The duration of the pulses and the intervals between them depend on the amplitude and frequency of the input signal. Formers 7 and 8 may optionally filter the input signals to eliminate high frequency components. From the output of the imaging unit 7, the signals arrive at the information input of the shift register 11, where they are time-sampled and delayed with a discrete step equal to the period of clock pulses fed to the clock input of the register 11 from the generator 9 through the frequency separator 12, achieving a smaller difference of two discrete values of the monitored level measured by the device, sampling and delaying the lead signal from the former 7 are performed twice. The first of these, with a larger discrete step, occurs on register 11 and the OR 13 elements, which unite the output groups of this register, and the second, with a smaller discrete step, on the register 18. The clock period for the register 11 is set so that the discrete step The signal delay was approximately half the period of the high-frequency components of the input signal. If there is a single signal at the information input, the units 11 are recorded in the register 11, and zeros in the intervals between them. As the logic units and zeros advance through the register 11, they appear at the output of each bit element, from where they arrive through the group OR 13 elements to the input of the keys 14. In addition, the signals from the first output of each group of outputs of the register 11, combined by elements OR 13, arrive at the inputs of the switch 16. Depending on the address code supplied to the address input of the switch 16, the signals pass from one or another output of the register 11 through the switch 16 and the public key 17 to the information input of the shift register 18 to the clock one od pulses which are supplied from the generator 9. The clock may come directly from the generator 9 (as shown in Figure 2) or through a frequency divider with less than the divider 12, the division ratio. The elements OR 15 receive signals to the first inputs of the matching elements 19, either from the outputs of the public keys 14, or from the bit outputs of the register 18. Signals from the output of the imaging unit 8 are simultaneously transmitted to the second inputs of all the matching elements 19 through the matching element 10, where sampling the signals with the oscillator frequency 9. If the third inputs of the elements 19 match a single signal from the control unit 2, groups of pulses appear at their output at the counting inputs of counters 20. Intensity the occurrence of pulses (the average number of pulses per unit time) is maximum at the output of that element 19 of coincidence, on which the signal from sensor 5, held by registers 11 and 18, coincides with the signal from sensor 6. The magnitude of the shift, which characterizes the height of the monitored level, is determined by the number of the counter 20 with the largest number of pulses accumulated during the measurement time. The magnitude of the value in relative to the time shift of the signals is expressed by the number of clock pulses, which is delayed by registers 11 and 18 from the sensor 5 until it co-operates with the signal from sensor 6. The measurement process is carried out in two stages. At the first stage, according to the number of the counter 20 with the largest number of accumulated pulses, the time separation of the input signals from sensors 5 and 6, expressed by an integer number of clock cycles Ti of the delay signal, is determined. At the same time, to the first inputs of the coincidence elements 19, signals are supplied from the outputs of the shift register 11 through the elements OR 13 and 15. When the control inputs of the keys 14 are received a single signal from the first output of the control unit 22, and to the control key input 17 - a zero signal from the second output of the block 22. If there is a single signal from the driver 7, delayed by the shift register 11, from the driver 8 and the third output of the block 22, at their outputs, sampling pulses appear, counted by counters 20 until the moment of overflow of one of them. The number of pulses at the output of the coincidence element 19 is proportional to the duration of the coincidence of single signals at its inputs. The duration of such a match will be the longest on that coincidence element 19, at which the delay time of the signal from shaper 7 coincides (taking into account discreteness error) with the delay time of the signal from shaper 8. The resultant counter 20 connected to this coincidence element 19 will overflow before the other counters . The discreteness step P of the signal delay from the generator 7 at the first measurement stage is determined by the period T0 of the oscillator pulses 9, the divider frequency division factor Ki 12 and the number m of the register 11 outputs in the group connected to one element OR 13. So, if the outputs of the register 11 shift divided by the number of counters 20 into eight groups, and their number in each group m is 4, the period T0 is 0.25 ms, the division factor is Ki 2, then the discrete step of the signal delay from the driver 7 will be directly at the outputs of the register 11 TI KiT0 0.5 ms, and out ode of elements OR 13 Ti vmax / b Ti -m 2 ms. In the case when the time difference 0 of the input signals, for example, when the height of the Z0 level is 19.84 m is 10.7 ms, before others the counter 5 overflows, where the largest number of pulses accumulates. Taking into account the origin (from the zero output group), five clock cycles Ti will pass by the time in (fig. 3a), corresponding to the beginning of the fifth group of outputs of register 11, which is connected with the score card 5. Therefore, the result of the first stage gives a rating of 6 mutual separation of signals, which is in the range of 02 2Th in 6Ti, i.e. in the interval of Ti duration 2 ms. At the same time, the difference in the values of the material levels corresponding to the values of in ml & i is equal to, AZi Zi-Z2 is 23.4-14.0 9.4 m. The signal from the overflow output of the counter 20 is fed through the information input of the control unit 22 to the information input of the memory register 23 and through the OR element 24 to the input of the coincidence element 26, allowing passage through it and the OR element 27 clock pulses to the input of the distributor 28 pulses received through the synchronization input block 22 from generator 9. In the initial state, a single signal is present only at the zero output of the distributor 28, from where it is fed through the third output of block 22 to 0, the third inputs of the matching elements 19. With the arrival of the first Tat pulse, a single signal at the zero output disappears and appears at the first output of the distributor 28. At that, further passage 5 pulses through the coincidence elements 19 are stopped and the state of the counters 20 is fixed, in which a single signal at the output of the overflow of one of them is saved. From the first output of the distributor 29, the signal enters through the open element 20, coincides with the zeroing input of trigger 32, translates it into a state where a single signal is present at its inverse output, and into the control input of the register 23. With this signal, the number code is written to register 23 overflow of the counter 20, which is present at the information input of the block 22. From the output of the register 23 this code enters through the address output of the block 0 22 to the address input of the switch 16 and the first information input of the unit 21 for storing and processing measurement results. By the second clock pulse, the distributor 28 is transferred to the state where a single signal appears only at its second output, from where it is fed through the open coincidence element 33 to the trigger setup input 29 and brings it to a new state. In this case, the single signal coming from the inverse output of the trigger 29 to the input of the coincidence element 30 and through the first output of the block 22 to the control inputs of the keys 14 disappears and appears on the non-inverse output, from where 5 to the input of the matching element 31 and through the second output of the block 22 to the input of the control of the key 17. With the arrival of the third pulse, a single signal appears only at the third output of the distributor 28. This signal opens the coincidence element 25 and through the fifth output of the block 22, the counters 20 are reset. A single signal at the overflow output 5, the counter 20 disappears and the coincidence element 26 closes, so the next clock pulse passes through the open coincidence element 25. By the fourth clock pulse, the distributor 28 switches to the initial state and a single signal. appears at its zero output, from where it is fed to the coincidence elements 19. In this case, the single signal from the third output of the distributor 28 to the input of the coincidence element 25 disappears (the switch 28 is switched by the falling edge of the clock pulse). The initial state of the distributor 28 is maintained until the next overflow of one of the counters 20. From the moment a single signal arrives from block 22 to the third inputs of coincidence element 19, the second measurement stage begins, where the overflow number of counter 20 determines the amount of mutual shift of input signals only between the values of в and $ 2 of the delay signal, and the discretization step is Ta equal to the period of the clock pulses arriving at the clock input of the register 18. The measurement process proceeds in the same way as in the first stage, but with the difference that the first strokes of the elements 19 of the coincidence signal are given through elements OR from the outputs of the register 18 shift. The information input of the register 18 receives signals through the switch 16 and the public key 17 (from the first output, i.e. from the low-order output) of the group of outputs of the register 11, the number of which coincides with the number of the counter 20, which is full in the first measurement step, The second measurement stage ends when a single signal appears at the overflow output of one (or several) of the counters 20. This signal goes to the second information input of the storing and processing unit 21, as well as through the information input of the block 22 and the OR element 24 to the input of the element 26 match. As a result, the control unit 22 starts operating as described above, but already under a new state of the flip-flops 29 and 32. The single signal disappears at the zero output of the pulse distributor 28, thereby fixing the state of the counters 20 and appearing on its first output, from where it is fed through the open match element 31 (the match element 30 is closed), to the input of the trigger setup 32 and the control input of the block 21. With this signal in block 21, the overflow number code is recorded at the first stage of the counter 20 arriving at the first information move unit 21 from the output register 23 and the code number counter 20, the overflow in a second step the measurement, which is present on the second information input unit 21. When this unit is used or the code to the overflow output of counters 20, or other code. formed if necessary from the specified unit code. The trigger 32 is switched to a state where a single signal from its non-inverse 5 output opens the coincidence element 34. Therefore, the single signal arising in the next cycle from the second output of the distributor 28 enters through the coincidence element 34 to the zero reset input of the trigger 29 and 0 puts it in a state where a single signal appears on the inverse output. In this case, the key 17 and the match element 31 are closed, and the keys 14 and the match element 30 are opened with a single signal with 5 inverse trigger output 29. When the third and fourth clock pulses arrive at the input of the distributor 28, the process described above, the circuit returns to its initial state, from which it starts another regular measurement cycle. The initial setting of the initial state of the meters 20 and the control unit 22, for example, when the power is turned on, is performed automatically or manually (not shown). 5 The codes of the numbers of the meters 20, fixed in block 21, overflowed in the first and second stages of measurements, give an estimate of the value in the delay of the leading signal from the sensor 5 to coincide with 0 by the delayed signal from sensor 6, expressed by the number of delays in both registers, in the form of 9 jiTi + (J2 + 0.5) T2, where ji, J2 are the numbers of overflowed counters 20, respectively, in the first and second stages 5 measurements. In the first term of this estimate, the unknown value in is identified when measuring with the nearest lower or equal quantization level when the signal is delayed at register 11, and in the second 0 term - with the closest quantization level with an additional delay of the signal on register 18 (an increase of J2 by 0.5 takes into account the compensation of the systematic quantization error) Then the error of the discreteness of the estimate in takes values in the range of -T2 / 2 + T2 / 2, and its expectation is zero with a standard deviation equal to, due to the same 0 probability of occurrence of values of the unknown value of the mutual shift of the input signals within one step discretization T2. Under the conditions of the above example 5 discretization step T2 T0 0:25 cm (since the second frequency divider is absent, the division factor is K2 1), signals to the information input of the register 18 at the second measurement stage are received from the first output of the fifth group of outputs rep-tyrosis 1 {from its 20th bit yes), the maximum value of the delay on the eighth; -; The register bit 18 is different 8 x 0.25 2 ms, i.e. the value of T.;, when measured by n,; jano; ih4r fi from the others counter 2. on which: -h ;; yP ;; 1Vyyts the largest number, Mg: pulses (.o5,;. At the razkulkaty echenkz values of engirt pkgie yuz - 5T, 4 (+2 0, B) Tz - s, and the estimate of the height of the level of FED: - h- |, t ., с о к р-тг н л vi g: ь to the value , |. .itg-lse: -gmo decreased; -, i.y; :, n-3 "- .. viX yCTppiiCT-;. ; : i; ;.; :: eel -; h ;;: -; l, :: v;. TOP SCENE; .A b1 0 -% ii f-к :, and the error AZ-Z. With the use of counters i 0 and evil: -mix 19 .. coincidence (cap in the prototype) the errors are / V9- (5K), 5jTr - 0.3 hp, / jZ, -lif / i, i.e. arast at OTHER CONDITIONS 3 RZZE. FOR the same; and; and about the prototype of the result, the hypered device, consequently, –u- ij -j h;; is supported by the account “t h) r z P je 1 . -l -, ..., silt nitel'ma obra; j. calculating the values of the 2. polished time level: - L (Y according to the reference system Z fi 61), matte; hе re: 7K: 1st; It has adjacent cycles with the goal of yiCK. noMfM-i / iii of erroneous results, in a ml of mlnd, preparation for the preparation and further processing of the mtp. Thus, the recording of ochulgates in block 21 is occupied by cpssH jre.iiuHo wano voemnii (one period of Tx; nd all: “; 1.p:, -; zm zr an), their processing can be wasp; destallt (: simultaneously with the process -1z; - 1:; re n-:. CD with a p / m of a / s of the system 1. Device for discrete control of the level of lumpy materials in underground tanks, containing two sensors of seismic capacity, dead sound mechanically, through a talus of a proud array with a capacity and connected to the measuring unit, the dztchkm are located on different piiCcrosHWi i from the lifting capacity:, measuring | 6 / uk consists of the first m of the second form-L1 f .; gko: lei impulsoo, the inputs of which are UND ;; LUMB; via the vapor / agora inputs measure-01, -bite bloc:; and x to the second and second dach-h coz; G: “-; er, h“: x oscillations, geno-T0f) .- i Tci.cros;.;: ;; г .. о ",. tselitel of frequency, pvoneg-D ovgmst L-sGr; -; ha; email. copp day, counters, memory unit and processing connected to the outputs of the counters, the output of the first driver connected to the information input of the first shift register, the output of the second driver to the first input of the first element of the joint, the generator output to the second trigger of the first match element and through the divider frequencies to clock echo first the sdzigz register, the second inputs of the remaining match matches are connected to the output of the perceptive coincidence element, and their outputs J are to the counting inputs of counters, the outputs of which are connected to the races of the multi-input elements of the ML I. It is also due to the fact that, for the purpose of noauLu "i-ivin resolution, two-input OR elements are connected to it, connected by inputs to output groups the first shift register, and the outputs through the first keys and further through the two-input elements OR to the first inputs of the matching elements, the number of which and the number of counters associated with them are equal to the square root number of controlled discrete levels, switch outputs connected by inputs to the first outputs of the first shift register in each group, the second shift register connected by information the input through the second switch output to the switch, the clock input to the generator, and the outputs to the second inputs of the two-input OR elements, and the control unit, through the information inputs of which the overflow outputs are connected, the counters with the inputs of the multi-input element OR, the synchronization input of the control unit is connected the generator output, while the memory and processing unit is provided with two informational inputs, one of which is connected to the overflow outputs of the counters; the other and together with the address input of the switch to the output output in the control unit, first control output by:,; Lednov connected: the control inputs of the-first key, the second output - to the control zhodu second key, the third output - to the third inputs of the coincidence of elements associated with the counters, the fourth output - to at the entrance of the plant, in the form of an order and for the order, and the fifth exit, to the inputs for resetting the counters. 2. The device according to claim 1, of tl and h zyu sch e there with that the control unit is made in the form This register is connected by the information input to the information input of the control unit, and by the output to its address output, pulse distributor, first and second triggers, element of coincidence, whose first and the second is connected by the first inputs to the synchronization input of the control unit, and the outputs via the OR element to the input of the pulse distributor, the second input of the second coincidence element is connected to the output of the multi-input element OR, the zero output of the pulse distributor is connected to the third output of the control unit, the first output is through the third and the fourth match elements — to the inputs of zeroing and setting the first trigger, connected respectively to the control input of the register and the fourth output of the control unit; The fifth and sixth elements of the output match to the installation and zeroing inputs of the second trigger, the third output to the second input of the first match element and the fifth output of the control unit; the inverse and non-inverted outputs of the first trigger are connected to the second inputs of the fifth and sixth match elements , and the inertial and non-inverse outputs of the second trigger are connected to the second inputs of the third and fourth coincidence elements associated with the first and second outputs of the control unit, respectively.  /. Q I  "Iffi3 & % ESR OPMA Ш № / /// & / // & // $ / Л k Ye / f // & // & / // Ф // / ж // & // $ // / А Fig. f SdVig signals 8 OS s en HI Byso / by level Vi / Sloppulso§ $ FIG. four