SU1693613A1 - Digital filter - Google Patents

Abstract

This invention relates to digital computing and is intended for use in digital signal processing systems. The purpose of the invention is to increase speed. The filter contains M computational modules (M is the order of the filter), Each module consists of multiplier 4, p-bit adder 5, t-bit elements 6 and 7 of the delay, p-bit element 8 of the delay, single-bit element 9 delays and t-razdny adder 10.2 Il,

Description

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This invention relates to digital computing and is intended for use in digital signal processing systems.

The purpose of the invention is to increase the speed of the digital filter.

Fig, 1 shows a functional diagram of a digital filter; figure 2 - functional diagram of the computing module of the digital filter.

The digital filter (figure 1) contains a computing module 1, information inputs 2.1 and 2.2 and information outputs 3.1 and 3.2. The computational module (Fig. 2) of the digital filter 1 contains a multiplier 4, a p-bit adder 5, t-bit delay elements 6 and 7, a p-bit delay element 8, a one-bit delay element 9, m-bit adder 10, t-bit first input 11 module, t-bit second input 12 module, m-bit first output 13 module, t-bit second output 14 module.

The filter works as follows.

Let on the l-th clock pulse (at the i-th instant of time) the input count xk (i, k are arbitrary integers) arrives at the information input 2.1 of the digital filter. It is set at the inputs of the multipliers 4 of each j-ro module, d). Synchronously with the input sample, the second inputs of each J-ro module are set to the lower-order bits (k-1) -ro of the partial result. In the i-th cycle, xk is multiplied by the corresponding coefficients aj and summation p of the lower digits of the product xk aj and p the least significant bits of the (k-1) -ro partial result of the delay element 8. By the end of the 1st cycle, the summation of the adder 5 is completed and the m most significant bits of the new k-ro partial result are set at the second output of the j-ro module. While summing up in the adder 5 j-ro module (, d), in the adder 10 () ro module are summed up the highest t of the product bits xk aj-i and the senior m bits (k-1) of the th partial result. By the end of the i-ro-touch, the summation in the adder 10 ends, and the m most significant bits (k-1) -ro of the partial remainder are set at the second output of the 0-1) -th module. By the (1 + 1) -th clock pulse p the lower bits of the k-ro partial result are stored in delay element 8 and set at the corresponding bits of the second output of the j-th cell, d), the transfer signal from the p-th bit of the adder 5 stored in a one-bit delay element 9 and set at the carry input of the adder 10. At the same time

but with this, the higher m bits of the xk aj and m higher bits of the (k-1) -ro partial result from the output of the -th module, r are stored in delay elements 6 and 7, respectively. In addition, the (1 + 1) -th clock pulse to the input 2.1 of the device receives a new input sample

Xk + 1.

In the (1 + 1) -th cycle m of the most significant bits of the 10th output, xk aj are summed with m higher bits (k-1) -ro of the partial result in adder 10 and at the end of (i + 1) -ro cycle m bit The odd k-ro partial result is set at the corresponding bits 15 of the second output of the j-ro module ().

While summation is taking place in the adder 10 of the j-ro module, the product xy aj is formed in multiplier 4 and in the adder 5 p the least significant bits of this product are summed with p the least significant bits of the k-ro partial result from the 0 1H modulo g).

Further work of the proposed filter is similar.

Claims (1)

Invention Formula A digital filter containing M (M is the order of the filter) of the computing modules, the first and second outputs m-ro (, M-1) of the computing module being connected to the first and second inputs of the (m + 1) -ro computing module, the first and The second outputs of the M th computing module are respectively the first and second information outputs of the filter, the first and second information inputs of which are the first and second inputs of the first computing multiplier, the p-bit adder and the p-bit delay element, respectively. p-bit multiplier moves are connected to the first input of the p-bit adder, the information output of which is connected to the input of the p-bit delay element, the first input of the multiplier is connected to the first input of the computing module, the p-bits of the second input of which are bits the second input of the p-bit adder, the first output of the computing module is connected to its 50 first input, and the outputs of the bits of the p-discharge delay element are p-bits of the second output of the computing module, the second input of the multiplier is in One task for calculating the coefficient of the computational module, characterized in that, in order to improve speed, a lithium adder (p + rp is the size of the information being processed) is inserted into each computer module, one bit d20 25 thirty 35 40 45 delay element, two t-bit delay elements, while the outputs of the t-bits of the multiplier are connected to the inputs of the bits of the first m-bit delay element, the output of which is connected to the first information input of the t-bit of the adder, outputs The detectors of which are high m-bits of the second output of the computational module, high The m-bits of the second input of which are the inputs of the bits of the second t-bit delay element whose output is connected to the second information input of the m-bit adder, the transfer input of which is connected to the output of the one-bit delay element whose input is connected to the transfer output r-bit adder. 3.1 3.2 1