SU1688175A1 - Frequency meter - Google Patents

Abstract

The invention relates to radio engineering and can be used to measure the frequency of a harmonic signal. The purpose of the invention is to improve the noise immunity of the device. The frequency meter contains delay lines, multipliers, a divider and a non-linear conversion unit. The introduction of filters, squaring devices, multipliers and adders, as well as the formation of new functional connections, ensure the noise immunity of the meter with respect to noise interference. 1 il.

Description

The invention relates to radio engineering and is intended to measure the frequency of harmonic signals under conditions of additive noise interference.

The aim of the invention is to improve the noise immunity of the frequency meter.

The drawing shows a functional diagram of the frequency meter.

The device contains the first delay line 1, the second delay line 2, the first multiplier 3, the second multiplier 4, the divider 5, the nonlinear conversion unit 6, the first filter 7, the squaring block 8, the second filter 9, the third multiplier 10, the first adder 11, the third filter 12, the fourth multiplier 13, the second adder 14. the fourth filter 15, the fifth multiplier 16. The first delay line 1 is connected in series with the second delay line 2 and the first

multiplier 3, the second input of which is connected to the input of the first delay line 1, the first input of the multiplier 4 is connected to the output of the first delay line 1, and the second input is connected to the input of the first delay line 1, the first filter 7 is connected between the meter input and the input of the first delay line 1 in addition, the squaring block 8, the second filter 9, the third multiplier 10 and the first adder 11, the first input of the divider 5 are connected to the output of the first adder 11, and the output of the divider 5 are connected to the input of the first delay line 1 th nonlinear conversion unit 6, to the output of the second multiplier 4 nocflefloeateflbHO connected third filter 12. The fourth multiplier 13 and an adder 14. A second output of which is connected to the second input of divider 5, the output of the first multiplier are connected sequentially chetSP 3

with

but

with

00

 ate

the rotary filter 15 and the fifth multiplier 16, the output of which is connected to the second input of the first adder 11, the second inputs of the third, fourth and fifth 10, 13, 16 multipliers are interconnected and connected to the output of the divider 5, the output of the third filter 12 is connected to the third On the first adder 11, the output of the second filter 9 is connected to the second input of the second adder 14 and the third input of the second adder 14 is connected to its first input.

The device works as the next cut. The mixture of signal and noise passes through the first filter 7 with a bandwidth from zero to the frequency fe. Then it goes to the series-connected first and second delay lines 1, 2, which have the same delay time m 1 / 2fe. After block 8, squaring the second 4 and the first 3 multipliers, we obtain respectively

(t) + n (t) 2

(one)

(t) + n (t) IS (t-T) + n (t-T), (2)

U3 S (t) + n (t) S (t -2 r) + n (t-2r), (3}

where S (t) V cos 0) 1 is the useful signal; 30

n (t) band-limited white noise with the autocorrelation function of the form

sin 2 yrfijr

Pn (tr)

2 f in

35

V is the signal amplitude;

a) - signal frequency;

t is the delay time.

The second, third and fourth filters 9, 12, 15 of the lower frequencies identify the constant components of these voltages. The averaging time in the filters is sufficiently long, the signal and noise are not correlated. Taking into account that the noise samples separated by the interval m are also not correlated, after the filters we get

U4 Ui 0.5V - +, U5 U2 0.5 V2cos tar, U6 Oz 0.5 V2 cos 2 cur.

where o is the noise dispersion within the band from zero to tv and the top line means the averaging of the signal in the filters. The voltages at the outputs of the first and second adders 11 and 14 are respectively

U7 IUU9 + U5 + U6U9, Ue U4 + 2U5Ug.

(7) (8)

5 The output voltage of the divider 5 is proportional to the ratio of the input voltages

ug

 U7 U4Ug + Us + Ue Ug

Us

Sh + 2 U5 Ug

(9)

After substitution of (4), (5), (6) in (9) we get

15

1 | Q P1 + U9 () U9 / 0 + 2U9pi

(YU)

20

where re, 1 + 2 02 / V2; cos 2 ca r.

p - cos (or; pi

The part of the device that includes the squaring block 8, the multipliers 3, 4, 10, 13, 16, the adders 11, 14, and the divider 5 are an analog solver that determines the voltage Ug from (10). The drive (10) to the quadratic equation. The solution is

Ug

(eleven)

After direct substitution, (10) and (11) become identities if

Ug -pi cos (Dt.

Thus, the voltage Ug at the output of the divider 5 is the count of the normalized autocorrelation function of the useful signal S (t) V cos when shifted in time by D t g. This voltage T oo does not depend on the amplitude of the input signal not from

interference level o2. After the nonlinear converter 6, the output voltage of which is related to the input voltage by the expression

one

2l: g

arccos Ug,

(13)

we get the frequency estimate

l

Uniqueness of frequency measurement is provided under the condition

0

Compared with the prototype in this device, the voltage proportional to the frequency 1 e does not depend on the dispersion

O2 noise, then the frequency estimate is unbiased.

Claims (1)

Invention A frequency meter comprising first and second delay lines connected in series and a first multiplier, the second input of which is connected to the input of the first delay line, in addition, a second multiplier, the first input of which is connected to the output of the first delay line, and the second input is connected to the input of the first delay lines, divider, adder and nonlinear conversion unit, characterized in that, in order to improve noise immunity, the first, second, third and fourth filters, the third, the fourth, are introduced into it, fifth ne (14) multipliers, a squaring block and A second adder, with the first filter connected between the input of the device and the input of the first delay line, is connected to the input of the first delay line sequentially (15) the squaring block, the second filter, the third multiplier and the first adder, the first input of the divider are connected to the output of the first adder, and the output of the 10 switch are connected to the input of the nonlinear conversion unit; the third filter, the fourth multiplier and second adder whose output 15 is connected to the second input of the divider, the fourth filter and the fifth multiplier are connected to the output of the first multiplier, the fifth multiplier is connected to the second input of the first summator, while the second inputs of the third, fourth and fifth multipliers are interconnected and connected to the output of the divider, the output of the third filter is connected to the third input of the first adder, the output 25 of the second filter is connected to the second input of the second adder, and the third input of the second adder is connected to its first input.