SU1683020A1 - Device for interfacing processor with memory - Google Patents

Abstract

The invention relates to digital computing and can be used to create permanent reprogrammable memory devices in microprocessor systems and microcomputers. The aim of the invention is to expand the functionality of the device by providing the ability to operate in a random data mode. The goal is achieved by introducing an address switch, an output select decoder, and a chip select decoder into the device containing the memory block, the mode register, the address counter and the address decoder and control commands. 2 tab., 2 Il.

Description

The invention relates to digital computing and can be used to create permanent reprogrammable memory devices in microprocessor systems and microcomputers.

The aim of the invention is to expand the functionality of the device by providing the ability to work in random mode,

FIG. 1 is a block diagram of the device; in fig. 2 - functional circuit of the chip select decoder.

The device contains (Fig. 1) a mode register 2 connected to memory block 1, an address counter 3, an address decoder and control commands 4, an address switch 5, an IC selector decoder 6, an output select decoder 7. Fig. 1 shows a group of information inputs-outputs 8 of memory block 1, a group of address inputs 9,

information input 10 of the device, first-third outputs 11-13 of the decoder 4, inputs 14, 15 and 16 read, write and reset the device, groups of outputs 17-20, set the programming mode, address, select the chip and select the output device, the fourth output 21 of the decoder 4, the group of outputs 22 of the counter 3 addresses, the second group of outputs 23, the first to third outputs 24-26 of the register 2 of the mode, the input 27 of the memory access signal, the fifth and sixth outputs 28 and 29 of the decoder 4,

The decoder 6 chip selector contains (Fig. 2) the decoder 30, the switch 31 and the element OR 32.

The device works as follows.

Memory block 1 consists of several groups of memory chips. In the general case, the memory chips within each group are combined by the output resolution, chip select and programming inputs. All address inputs of all the memory chips are combined and connected to the corresponding lower bits of the outputs 18 of the address switch 5, in addition, all the memory chips are integrated by the programming voltage inputs, in FIG. 1 not specified. Such an organization of memory block 1 allows, in all modes of operation of the device, to select simultaneously all the chips within one group and thereby write and read the information word in the write or read cycle and erase all the chips in the corresponding group in the erase cycle. The lower bits of the outputs 18 of the switch. The 5 addresses are used to select a memory location within the group of memory chips of the memory 1 unit: pi, the higher bits of the outputs 18 of the health switch 5 are used to select groups of memory chips of the memory 1,

The device provides reading of information from memory block 1 in the modes with sequential and random sampling of data and recording and erasing in the mode with sequential sampling of data.

In the sequential data retrieval mode, the address to the address inputs of memory block 1 and decoders 6 and 7 is transmitted via address switch 5 from outputs 22 of address counter 3, the state of which can be sequentially changed from zero, memory block 1 address or randomly selected the starting address of the read data array to the arbitrarily chosen end address of the read data array. In the general case, the information capacity of memory block 1 may exceed the capacity of the processor's direct-addressable memory, determined by the width of the processor's address, while the size of the read data array with sequential data sampling may be no more than direct addressable processor memory. In this case, the device occupies three addresses in the processor's address space, called the status register, the data register, and the address register. Physically, these addresses are respectively the register 2 modes, the information inputs / outputs 8 of the device, and the count lx 3 addresses. In the sequential data retrieval mode, the write or erase modes are set via the status register, the data register is read or written to the memory block, the address register is written to the address counter 3, the starting address of the read data array, and the number is read

or written words are controlled by the processor programmatically.

In the mode with arbitrary sampling of data the address to the address inputs of block 1

memory and decoders 6, 7 are transmitted through the switch 5 addresses from the output group 23 of the register 2 mode and the input 9 of the device address, and the entire memory block 1 is divided into pages, the number of which is determined by the number of bits of the output 23 register 2 mode, and page capacity is determined by the number of address bits supplied to the inputs. In random mode, the device takes up

5 address space of the processor, an address zone equal to one page of memory block 1; moreover, by changing the state of the outputs 3 i-ci meters 2 modes at the state register address, the processor can read

0 block size 1 memory w, i.e. select sequentially or in random order all pages of memory block 1. At the same time, the switch 5 of the address is always switched on for the translation of the address from the outputs 22 of the counter 3 of the address

5 and only in read mode with random sampling of data, the switch 5 of the signals from the output 21 of the decoder 4 of the address and control commands is transferred to the translation of the address from the device inputs 9 and the outputs 23 of the mode 2 register.

Consider the operation of a memory device for use in memory block 1 of memory chips with electrical recording and erasing information.

5 КР558РР2 6KO 348.348-02 TU. In the STOV case, the programming inputs of memory block 1 are absent and the output group 17 of register mode 2 is not used.

The operation modes of memory block 1, depending on the output signals, are given in gab. 1. The state of the bits of the register 2 mode and the input 27 of the signal of the recording cycle of the device, depending on the modes of operation of the device, are given in Table. 2

5When power on for gathering 10

A device reset should supply with a reset signal, zeroing the register 2 modes and the counter 3 addresses. This is necessary in order to put the device into storage and readiness mode, as well as to ensure that data can be read from the zero page of memory block 1 in the random data mode, from the zero address of memory block 1 in mode

5 with sequential data sampling.

Reading information from the device is carried out in a cycle processor input (not shown in the figures),

In the initial state, the memory chip of the memory block 1 is in the

storing information in accordance with Table 1. The processor at the inputs 9 of the device address sets the address of the memory cell of memory 1 in the random-sampled mode or the register of the data in the sequential-sampled mode, while the address must be held loop input. The address goes to the address inputs of the decoder 4, it is decrypted by it as the device address, and in a random data mode, single-level signals appear at its outputs 21, 28, and in a sequential-sampling mode - only at output 21. At the first In the case of the address inputs of the memory 1 and the decoders 6, 7, the addresses are transmitted from the inputs 9 of the device address and from the group of outputs 23 of the mode register. In the sequential sampling mode, the address is transmitted from the outputs 22 of the address 3 of the address, and one of the outputs 19 of the decoder 6 of the chip selection corresponding to the selected group of memory chips of the memory 1, a zero sampling signal appears. Next, the processor at input 14 of the device reads the input signal, which is decoded by the decoder 4 as a read signal from memory 1, and a single level signal appears on outputs 12, 29 of the decoder 4 in a sequential sampling mode and only on Exit 29 of the memory sample in random mode. At the same time, at one of the outputs 20 of the decoder 7 for selecting the output, the signal for selecting the corresponding group of memory chips of the zero-level memory block 1 appears, the memory block 1 is switched to the read mode, and read data appears at its input-output. Next, the processor reads the data from the device inputs-outputs 8 and removes the input signal from the device input 14 and the address from the device address inputs 9. In this case, the memory block 1 is transferred to the storage mode, since the signals from the outputs 19 and 20 of the chip selector 6, 7 and output are removed, and in the mode with sequential sampling of the signal at the output 12 of the decoder account 4 address and control commands change the contents of the counter 3 addresses per unit. After that, the device is ready for the next processor cycle.

Information is recorded in the register 2 mode, the address counter 3 is carried out in a cycle, the processor is output by the addresses of the state register and the address register, respectively. In the address part of the cycle, the output operation of the device is carried out similarly to the address part of the cycle input when accessing the device data register. Next, the processor sets the data at the information inputs 10 of the device, which arrive at the information inputs of the register 2 mode and the counter 3 addresses, and then the signal Output at the input 15 of the device, which is decoded by the decoder 4 so that its output 11 appears a signal of a single level when writing to the counter 3 addresses or at output 13 - when writing to the register 2 modes. As a result, data is written to these blocks. Next, the processor removes the signal Output, data and address from the corresponding inputs of the device and thereby ends the cycle output of the access to the device.

Before writing data to memory block 1, the processor prepares the device for a recording mode, in which the memory chips of memory block 1 are transferred from the storage mode to the selection mode in accordance with Table. 1. To do this, a code is entered into the device status register, in which the unit-level signal appears only at the second output 25 of the mode register 2. This signal is fed to the first control input of the decoder 6 chip selector, i.e. arrives at the control input of the switch 31 and the first control input of the decoder 30. At the same time, the output of the OR element 32 is connected to the output of the switch 31, and all the outputs of the decoder 30 are switched to the zero level, i.e. At the chip select inputs of all groups of memory chips of memory block 1, zero signals are set, and memory block 1 itself is set in accordance with Table. 1 is in non-selection mode. Only after this, the programming voltage is applied to the memory block 1, otherwise, if all signals are selected for a single-level chip, then in accordance with the table. 1, after connecting the programming voltage to the memory unit 1, all the memory chips are immediately in the unauthorized recording mode.

After the programming voltage is applied to the memory unit 1, the processor in a cycle output to the data register address records information in the memory unit 1. In this case, the work is as follows. In the device, switch 5 is turned on so that address signals from memory block 1 and decoders 6, 7 are connected to address inputs from the counter 3 address, the processor sets the address of the device’s data register, and then the recorded data is respectively at the inputs

and device information inputs-outputs 8, and the recorded data at information inputs-outputs 8 of the device must be held further for the entire recording time, then the processor sets the Output signal, and then removes it, ending the device access cycle. By cut-off of the signal The output at the signal 27 of the recording cycle of the device, the processor sets the high-level cycle signal, which must be kept for the entire recording time, since the processor does not access the device during the recording cycle signal. In the device, the write cycle signal is fed to input 27 to the decoder 6 and through the element OR 32, the switch 31 to the control input of the decoder 30, at one of the outputs of which, in accordance with the address signals at its address inputs, a single level signal appears, time before the end of the signal of the recording cycle in accordance with Table. 1 begins writing data to the selected group of memory chips of memory 1 at a given address. At the end of the recording, the processor removes the write cycle signal and the unit level signal from outputs 19 of the decoder of the chip select. At this, the cycle of writing data to one cell of the recording ends. Next, the recording can be continued, and the address can be changed by writing data to the address 3 counter in the cycle, outputting the address of the address register, or the address can be automatically changed to the next one. address of the data register.

Erasing in block 1 of memory is carried out for several cycles displaying the address to the device according to the addresses of the address register and the status register. During erasing, the state of the address signals and data and the interrogation inputs and information inputs / outputs of the device is indifferent. In the first cycle, the output by the address register of the address is transferred to the counter 3 of the address code of the address selected for erasing the group of memory chips of memory 1. In the second cycle, the processor output to the address of the status register is forwarded the write resolution code in accordance with Table. 2, After this, the programming voltage is connected to the memory unit 1. In the third cycle, the output to the erase mode code is sent to the address of the status register in accordance with Table. 2. At the same time, the signal of the unit level additionally appears at the output 24 of the register 2 of the mode and arrives at the control input of the decoder 7, as a result at one of the outputs 20

A zero output selection signal appears to be selected for erasing the group of chips in memory block 1. In the fourth cycle output to the address of the state register

the erase mode code is sent in accordance with the table. 2. As a result, additionally, at the output 26 of the register 2 of the mode, a single level signal appears at the input of the decoder 6, which

through the OR 32 element and the switch 31 enters the control input of the decoder 30. As a result, at one of the outputs 19 of the decoder 6, a chip select signal of a single level appears and in accordance with the table. 1, at the inputs of the memory unit, the erase mode of the group of memory chips selected for erasing is set. Next, the processor counts the time required to erase, and upon its completion

removes the erase mode, forward in cycles output in accordance with the table. 2, first, the erase permission mode code, then the write enable, Further erasure of the memory block 1 can be continued

in this order or, if the erasing is completed, the programming voltage is removed from memory block 1, after which, in a loop, the output of the processor sets the mode register 2, putting the device into readout mode and information storage.

Claims (1)

Claims An apparatus for interfacing a processor with a memory, comprising a mode register and the address counter, whose information inputs are the information input of the device for connecting to the information output of the processor, and the reset inputs are the input of the device for connecting to the processor reset output, the address and control decoder, the information group and the first, second control inputs of which are the corresponding inputs of the device for connection to the group of address outputs and the read and write outputs of the processor, with the first, second and third outputs of the address decoder and control commands being connected to the write and count inputs of the counter, respectively the address and the recording entry of the mode register, the first group of bit outputs of which is the group of outputs of the device for connection to the group of inputs of specifying the memory programming programming mode, in order to expand its functionality by providing the possibility of operating in randomly sampled, an address switch, a chip select decoder and an output select decoder are entered into it, the output address counter group is connected to the first group of information inputs of the address switch, the second group of information inputs of which are connected to the device input group for connecting to the processor address output group and the second group of bit outputs of the mode register, the first, second and third bit outputs of which are connected respectively, to the enable input of the output select decoder and the first and second enable inputs of the selector decoder of the chip, whose output groups are corresponding conductive O groups device for connection to the groups of inputs and select the output of the selection the memory chips, the fourth, fifth and sixth outputs of the address decoder and control commands are connected respectively to the control input of the address switch and the synchronization inputs of the output selector and chip selectors, the groups of information inputs of which are connected to the group of outputs of the higher bits of the address switch, the group of outputs the lower bits of which is the device output group for connecting to the group of memory address inputs, the control input of the chip select decoder is the device input for connecting to the output of the processor memory access cycle signal. Table 1 table 2 Schi 1 fig 2 Editor T. Yrchikova Compiled by V. Vertlib Tehred M. Morgenthal Proofreader V.Girn to