SU1679535A1 - Device for displaying data on tv screen - Google Patents

Abstract

The invention relates to a display technique and can be used in radio and sonar, measuring devices using a three-dimensional image. The aim of the invention is to improve the quality of the displayed information by providing the ability to display embossed axonometric images. To do this, a device containing an information source 1, an interface unit 2, a synchronization unit 3, an addressing unit 4, a buffer memory unit 5, a television receiver 6 and a code converter 7 are introduced into the device, a progressive imaging unit 8, a screen memory unit 9 and an adder 10 with related communications. The introduction of blocks and links allows one line by line to analyze the image as the imposition of several flat reliefs and form reliefs in rows with a shift, taking into account the effect of partial mutual blocking of reliefs. 3 hp f-ly, 6 ill.

Description

SL OE SL

CPifg.f

The invention relates to a display technique and can be used in radio and sonar, measuring devices using a three-dimensional image.

The aim of the invention is to improve the quality of the displayed display by allowing the display of embossed axonometric images.

Fig, 1 shows a functional diagram of the proposed device; Fig. 2 is a view of an image on a television receiver screen; FIG. 3 is a functional diagram of a synchronization unit; figure 4 - functional diagram of the block addressing; Fig. 5 is a functional block diagram of a progressive imaging unit; Fig. 6 is a diagram for explaining the progressive image generation algorithm.

The device contains a data input unit (information source 1), an interface unit 2, a synchronization unit 3, an addressing unit 4, a buffer memory unit 5, a television receiver 6, a code converter 7, a building imaging unit 8, a screen memory unit 9, an adder 10. Input 11 is the installation input of the device. Figures 1, 3-5 indicate the first, second and third control inputs 12-14 of the synchronization unit 3, the first to tenth outputs 15-24 of the synchronization unit 3, the first and second information inputs 25, 26 of the addressing unit 4 , the first and second address inputs 27, 28 of the block 5 of the buffer memory, the second information input 29 of the adder 10, the fourth and fifth information inputs 30.31 of the addressing block 4, the first and second address inputs 32, 33 of the screen memory 9, the first information input 34 of block 8 of line-by-line image formation, first output 35 of block 8 of line-by-line form image vanilla, fourth exit 36 of block 8 of line-by-line image formation.

The synchronization unit 3 contains a quartz oscillator 37 connected to a clock counter 38 of the line elements, to the output of which the shaper 39 of the quenching damping pulse is connected. The output of the imaging unit 39 is connected to the clock input of the counter of 40 lines connected to the imaging unit 41 of the frame damping pulse. The inputs of the first and second dividers 42,43 frequencies are connected to the output of the quartz oscillator 37. The direct outputs of the first and second triggers 44, 45 are connected to the first inputs of the first and second elements 46, 47 And, to the second inputs of which the outputs of the dividers 42, 43 are connected .

The first and second drivers 48, 49 pulses are connected to the outputs of the flip-flops 44, 45.

Unit 4 addressing contains the first and

the second switches 50, 51, the adder 52, the output of which is connected to the second input of the first switch 50. The output of the counter 53 of the shift is connected to the second input of the adder 52.

Block 8 line by line formation

The image contains the first code comparison node 54, a pulse counter 55 whose output is connected to the first inputs of the subtractive node 56, the second code comparison node 57 and the switch 58. The output A B of the second node 57 of the code comparison is connected to the control input of the switch 58, the output of which is connected to the D input of the counter 59 line number. To counter V-input 59

The counter 60 of the element number is connected. An output element 62B and an element 63 of delay are connected to the output AB of the first node 54 of code comparison through the pulse shaper 61. The source 1 of information and block2 of the interface form a block 64 data entry.

The principle of operation of the device is as follows. There is a three-dimensional array of information consisting of MxN elements, each of which has an amplitude in the range of 0 ... 2p-1, i.e. the amplitude is represented by an r-bit binary code. On the screen of the television receiver 6, it is necessary to display an axonometric projection of the three-dimensional image. It is obvious that the number of display elements on the screen horizontally must be greater than M, namely M + m, where t is the horizontal shift of the image, and vertically the number of elements must be

more than N, namely N + rt, where n 2p-1 is the margin to display the amplitude (figure 2). In order to highlight the difference between high amplitude elements and low amplitude elements, it is necessary

Enter different either in brightness or in color of the displayed items.

The image (Fig. 2) can be considered as the superposition of N flat reliefs, the first one standing on the first

line below, partially covers the second relief, standing on the second line below; the second relief, in turn, partially covers the third one, standing on the third line, etc. But at the same time, each following relief is shifted one element upwards

relative to the previous relief and for some distance to the right. It is clear that an element of large amplitude (for example, A) standing on the first line will close

And the lines are higher, no matter what amplitude the elements are on these lines along this horizontal coordinate. In the middle lines of the image, the picture is even more complicated: if the maximum amplitude of the relief is n 2p-1, then it is necessary to analyze the selected horizontal coordinate amplitude on the n lines preceding the given line of the image.

The information display device operates as follows. There are three modes of operation: 1) transferring data from source 1 of information to block 5 of the buffer memory; 2) analysis of the formation data and its recording in the screen memory block 9; 3) data indication on the television receiver 6 in read mode from screen memory unit 9. Modes 1 and 3 are compatible in time, t, e, while data is being displayed, new data can be received in block 5 of the buffer memory. Modes 2 and 3, in principle, can also be combined if you double the volume of block 9 of the screen memory and write data in one half, read from the other, and then swap them.

Mode 1 starts by applying a trigger pulse from interface unit 2 to synchronization unit 3 at its input 12. This pulse arrives at the S input of trigger 44 (FIG. 3) and starts it. A logical 1 pulse from the direct output of the trigger 44 is fed to the input of the element 46 I and allows the passage of frequency pulses fi from the frequency divider 42 to the output 18 of the synchronization unit 3. From the output 18, the clock pulses of the frequency fi arrive at the first control input of the addressing unit 4 (FIG. 4) and then to the clock input of the shift counter 53. Simultaneously with the inverse output of the trigger 44, the potential of the logic O arrives at the output 19 of the synchronization unit 3. This potential enters the second control input of the addressing unit 4 and unlocks the counter 53 via the R input. The counter 53 starts counting the frequency pulses fi from zero. At the same time, the potential of the logical O from the control input 19 of the addressing unit 4 is fed to the V-control input of the first switch 50 and switches it to the state when the output of the adder 52 is connected to the address input 27 of the buffer memory block 5, and to the input 28 of the block 5 is connected input 26 of block 4 addressing. From the outputs of the first comm / tatoa 50, the write addresses for block 5 of the buffer memory are removed. Thus, the write addresses on the inputs 27, 28, block 5 are formed from the addresses on the inputs 25, 26 of the addressing block 4.

The output of block 2 of the interface receives information in the form of MxN p-bit words.

By analogy with the television image, it can be assumed that the array of information has N lines, each line has M words (line elements), and the information is transmitted element by element until one line is filled; then the next line starts up, and so on. In block 5 of the buffer memory, this array is entered so that the row order (from 1st to Nth) is not violated, but as the line number increases, the information shifts along the direction of the elements so as to form an oblique quadrilateral in Fig. 2, in order to form a subsequent axonometric projection. For this purpose, a linearly increasing number from counter 53 is added to adder 52 to the horizontal address of input 25, which from the output of interface block 2 to input 25 of addressing block 4, in adder 52. Limits of variation of this number O ... t. Figure 2 shows how, over the course of the rows, the array is gradually shifted so that by the Nth row, the offset reaches m elements. Hence the shift frequency fi for counter 53 can

be defined as fi-d thst where

fcip int - frequency of transmission of information lines from the output of block 2 of the interface.

When the transfer of information from the interface unit 2 to the buffer memory unit 5 is completed, the output pulse of mode 1 arrives at the input 13 of the synchronization unit 3, which then goes to the R input of the trigger 44 and resets it. In this case, the positive front from the inverted output of the trigger 44 is fed to the input of the first pulse shaper 48, on which a pulse is formed that triggers the trigger 45 via the S input; the inclusion of this trigger indicates the beginning of mode 2.

Attention should be paid to one particular feature when writing information to block 5 of buffer memory in mode 1. Information from the output of block 2 of the interface arrives at the information input of block 5 of the buffer memory not directly, but through adder 10, where the p-bit information words are summed With the line number code (1 ... N), which comes from the output of interface block 2 to input 2641, the transit passage through addressing block 4 is fed to input 29. Thus, the information on the 1st line is incremented by one, the second line - two, ... on the Nth line - to N. This is necessary so that the prk analysis, each next line, as if rises above the previous one to create a perspective. Buffer memory block 5 in mode 1 is recording. Recording mode

is provided by supplying a logical O to a WR write control input (read) from the output 15 of the synchronization unit 3, where this logical O is removed from the direct output of the trigger 45.

Mode 2 (or analysis mode) and shaping begin immediately after termination of mode 1 by triggering trigger 45 of synchronization unit 3. With this trigger, four output signals of synchronization unit 3 are generated:

Claims (4)

1) at output 15, a logical 1 signal appears, which, arriving at the WR input of the buffer memory unit 5, puts it into read mode and, entering the third input of the block 8 of progressive imaging, opens element AND; 2) at the output 20 a logical O signal appears, which, arriving at the third control input of the addressing unit 4, is supplied to the control V input of the second switch 51, while information inputs 30 are connected to the information outputs 32, 33 of the second switch 51, 31 (write address of screen memory block 9); 3) at the output 23 of the block 3, pulses of the third frequency divider 43 appear, which pass through the element 47 And open logical 1.c of the direct output of the trigger 45; these pulses go to the fourth input of the block 8 of line-by-line imaging, and in it to the clock C-input of the counter 59 line number; 4) the output 24 of block 3 at the moment when the trigger 45 is turned on appears a pulse generated by the second pulse shaper 49; This impulse is fed to the second control input of the block 8 of the line imaging, and therein to the R inputs of setting the pulse counter 55 and the element number counter 60 to zero. In addition, since the start of mode 2, flip-flop 44 is reset to zero, the output 19 of synchronization unit 3 produces a logical signal 1, which, arriving at the second control input of addressing unit 4, locks the offset counter 53 and switches the first switch 50 to when the inputs 27, 28 of the block 5 pass address signals received at the inputs 30, 31 of the addressing block 4 (readout addresses of the buffer memory block 5). The combination of these signals is associated with transferring the buffer memory block 5 to the read mode, and the screen memory block 9 to the write mode. Since the readout addresses of the buffer memory block 5 and the write address of the screen memory block 9 coincide with the input 31, this means that the element number j is the same horizontally. The difference between the read addresses of block 5 (output 35) and the read of block 9 (input 30) is due to the fact that in the analysis of block 5 several elements are read vertically, and in the block 9 only one of them is recorded, The spatial image (see Fig. 2a) can be represented as the overlay of a set of reliefs, as if cut out from a thin material and arranged on 0 rows, and the relief of the first row is completely visible, the relief of the second row is raised upwards relative to the relief of the first row by one element vertically, i.e. one line of television image 5 relief of the third line is lifted by two elements, etc. In addition, the reliefs are gradually shifted horizontally with a resolution of one element horizontally (for example, if the relief is 192 and the maximum horizontal shift is m 64, then the horizontal shift is one row every element 192/64 3 lines. This makes it clear what is needed before recording the data array in the block 5 of the buffer memory to summarize 5 amplitude information with the line number address, and a progressively increasing shift added to the horizontal address. Image analysis and imaging 0 is reduced to determine the distribution of brightness (or color) on any 1st line of the television image of the television receiver b, depending on the information in the previous n lines 5 (reliefs) of the array recorded in block 5 of the buffer memory. Fig. 6 illustrates a simplified case of p 4. The brightness of the image on the i-th row is determined by the set of amplitudes of the information on lines 1a, 2a, 3 0 4a. Let j 1. On line 4a, the amplitude A4a O, on the line Beyond Asa 2. The line number (Over) shows how many elements vertically the given line is separated from the analyzed one (i-th). In order to dot noots to 1st 5 lines, you need to have an Azz amplitude of at least three, i.e. String by is discarded during analysis. On line 2a A2a 0 and, finally, on line 1a Aia 3, i.e. reaches the i-th line (even with an excess). But since 1 is a string 0 is for line 1a the following, then it is already covered by the first amplitude element. Therefore, in the 1st line of block 9 of the screen memory, the amplitude of An is recorded at j 1, FIG. Bg is shown at j - 1 count graph 5 lines of information on four positions. For example, with j 7 when analyzing the 1st row A4a 4, i.e. it immediately reaches the 1st line, therefore, when j 7, the amplitude of AI 4 is recorded. The graph of viewing lines in FIG. 6 with fa -1 consists of only one position. When you go to the (1 + 1} th line, the information on lines 16,26,36,46 is analyzed; when you go to the (1 + 2) -th line, the information on lines 1c, 2c, Sv, 4c, etc . Thus, the analysis algorithm is as follows: on the 1st line of the image in the jth element, the horizontal amplitudes of information in the previous n rows of the array, starting with the lowest, are analyzed. In the analysis, the amplitude in the (1-n) -th row of the array is compared with the number -n; if A (i-n) j2: (l-n), then in screen block 9, the amplitude Alj l-n is written to address I. This algorithm in block 8 is organized as follows. The number of the analyzed line (relief) i is determined by the state of the counter 55. At the beginning of mode 2, the counter 55 is set to zero by the R input from input 24 of block 8. The number of the analyzed element j of the line is determined by the state of the counter 60 of the element number also at the beginning of mode 2 is set to zero. The operation of block 8 for some arbitrary values of I, J is as follows. The device has an input 11 for setting the amplitude parameter, which is used to specify the number that determines the maximum amplitude of the information maximally on the vertical (in Fig. 2, n is indicated, and the relief of the uppermost line is placed on the screen - Fig. 2c ). This number arrives at the second B input of the second node 57 of the code comparison, the first A input of which receives the number I from the output of the counter 55. First, we can consider the general case when i max. Then at the output of the second node 57 code comparison is a logical 1, arriving at the control V-input of the switch 58. According to this signal, the switch 58 passes a number from its B-input, namely, Pmax, which goes to the information D-input of the counter 59 of the line number. At the V-input of the recording resolution of the counter 59, a pulse is output from the output of the delay element 63, and the number pmax is recorded in counter 59. At the output of the subtractive unit 56, the i-Pmax number appears. Through the output 35 of block 8, this number enters the third information input of the addressing block 4 and through the first switch 50 is used as the line number of the block 5 of the buffer memory operating in read mode. Information from block 5 of the buffer memory is fed to input 34 of block 8, i.e. to the A input of the first comparison node 54, where it is compared with the number of 1-pMax from the output of the subtracting node 56. If the amplitude of the information signal from block 5 is less than the difference I - Pmax, then the signal is on the (1-PMVx) -th line it does not reach the 1st analyzed line and it is necessary to go to the (1-pMvks + 1) -th line in block 5 of the buffer memory. At the output of the first comparison node 54, logical O is saved, the record in the counter 59 is not made, but the next pulse from the output 23 of the synchronization unit 3 arriving at the clock input of the counter 59 operating in the subtraction mode puts it into the pmax-1 state. At the output of subtractive node 56, the number 1-Pmax + 1 appears. At this address from block 5, a new information is output, which in the first code comparison node 54 is compared with the number 1-pMax + 1, and so on. Until at some regular counter of the counter 59, the code comparison node 54 will not give a logical G signal. In figbg counter clocks 59 correspond to the movement in the up arrow. Logical 1 from the output of code comparison node 54 starts shaper 61, whose pulse, passage through element 62, opened by mode 2 signal from output 15 of synchronization unit 3, arrives at output 36 of block 8 and further to WR input of recording enable of block 9 of screen A memory in which the number in from output 35 is written at address l, j to the inputs 30, 31 of the address. After the end of the recording, a pulse appears at the output of the delay element 63, through which 59 is again recorded number Pmax, and the counter 60 transitions to the state J + 1 - the analysis of the next element in the line begins (the delay time in element 63 is longer than the recording pulse duration generated by the pulse generator 61) After all the M + t elements in the line are analyzed (such is the capacity of the counter 60) , at the P-output of the overflow of the counter 60, a pulse appears, which is clock for counter 55, and it passes into the 1 + 1 state. After all N + n lines of the image have been analyzed (such is the capacity of counter 55), at the P-output of the overflow of counter 55 there appears a pulse coming from the fifth output of block 8 to the input 14 of synchronization unit 3 (to the R input of trigger 45). The trigger 45 is reset, and this ends mode 2. At the beginning of mode 2, when the number I in the counter 55 is small (starts with zero), then 1 Pmace. Then, at the output A B of the second node 57 of the code comparison, a logical O arrives at the control V-input of the switch 58, which passes the number of co / its A-input, i.e. i arriving at the information D input of the counter 59. When a pulse is applied from the delay element 63, the number is recorded in the counter 59. Then, at the output of the subtracting node 56, H 0 is formed, i.e. analysis and generation starts from the bottom zero line. Then, counter 59 goes to state 1-1, at the output of the subtracting node 56 i- (M) 1, and so on. After resetting the trigger 45 of the synchronization side 3, mode 3 starts - indication of data on the television receiver 6. At the output 20 of the synchronization unit 3, a logical 1 signal appears, according to which the switch 5 of the addressing unit 4 is switched to the output mode 32, 33 inputs 21, 22 are connected, taken from the line 38 counter elements of the line and from the counter 40 lines of the clock 3 synchronization. At the output 15 of the synchronization unit 3, a logical signal O appears, which blocks element 62 AND of block 8. Thus, the recording of block 9 of the screen memory is blocked and it operates in read mode. The image on the screen of the television receiver 6 has the character shown in FIG. 26, where the elements of the array with a large amplitude are distinguished by either brightness or color. The duration of mode 2 (Greg.2) is determined by the number of analyzed pixels (IVI-i-rn) (N + n), the number of analysis and generation cycles (average max / 2) m for one cycle, which is determined by the response time of the subtractor node 56 and first node 54 comparing tcr. codes, i.e. TRZZH.2 (M + m) (N + P). Thus, by introducing the adder 10, the progressive image forming unit 8, the display memory unit 9 with corresponding links, the quality of the displayed information is improved. Formula 1 of the invention. A device for displaying information on a television receiver screen, containing a data input unit, the first and third outputs of which are connected to the first and second information inputs of the addressing unit, the third and fourth outputs of the data input unit being connected to the first and second controls the synchronization block inputs, the first of which is connected to the write permission of the buffer memory block, the first and second address inputs of which are connected to the first and second outputs of the addressing block, the second and tr Tille outputs synchronization Christmas trees are connected to first and second television emnhrovhodam receiver, information input of which is connected to the output of the code converter, characterized in that, in order to improve the quality of the displayed information by providing the possibility of displaying embossed axonometric images, a progressive imaging unit and an on-screen memory unit are inserted into it; 0 whose information input is connected to the fifth output of the data input unit, the second information input of the adder is connected to the third output of the addressing block, the output of the adder is connected to the information input 5 to the input of the buffer memory block, the output of which is connected to the first information input of the building block of the image forming, the second information input of which is the installation input of the device, the first output of the block of line formation of the image "connected to the information input of the block of the screen memory and the third information input block addressing, the fourth and The 5th fifth informational inputs of which are connected to the second and third outputs of the block of progressive imaging, the fourth output of which is connected to the recording resolution input of the block 0 screen memory, the output of which is connected to the information input of the code converter, the first and second address inputs of the screen memory block are connected to the fourth and fifth outputs of the addressing unit, the first, second and third synchronization inputs and the sixth and seventh information inputs are connected respectively to the fourth, fifth, sixth, seventh and eighth outputs of the synchronization unit, 0 the ninth and tenth outputs of which are connected to the first and second control inputs of the building block of the formation of the image, the fifth output of which is connected to the third control input 5 of the synchronization unit, the first output of which is connected to the third control input of the block i of progressive imaging. 2. The device according to claim 1, wherein the synchronization unit contains a quartz oscillator, a row element count, a lower quenching pulse generator, a row counter, a framing quenching pulse generator, the first and second 5 Swarm frequency dividers, first and second elements. And the first and second triggers, the first and second pulse drivers, the output of the crystal oscillator connected to the clock inputs of the row element counter, the first and second frequency dividers, the outputs of the bits of the row element counter are the seventh output of the block, and the transfer output of the row element counter is connected with the inline quenching pulse input, the output of which is connected to the row input of the row counter and is the second output of the block, the outputs of the bits of the row counter are the eighth exit of the block, and the row count transfer is connected to the input of a frame extinguishing pulse generator, the output of which is the third output of the block, the first control input of which is the S input of the first trigger, and the second control input R input of the first trigger, the direct output of the first the trigger is connected to the first input of the first element, the second input of which is connected to the output of the first frequency divider, the output of the first element I is the fourth output of the block, the inverse output of the first trigger is connected to the input of the first pulse shaper whose output is connected to the S input of the second trigger and is the fifth output of the block, the third control input of which is the R input of the second trigger, the forward output of the second trigger is connected to the first input of the second element, And to the input of the second driver pulses and is the first output of the block, the inverse output of the second flip-flop is the sixth output of the block, the output of the second frequency divider is connected to the second input of the second element AND, the output of which is the ninth output of the block, the output of the second pulse shaper is the tenth output of the block. 3. Pop-up device 1, characterized in that the progressive imaging unit contains first and second comparison nodes, a pulse counter, a line number counter, an element number counter, a subtracting node, a switch, a pulse driver, an AND element and a delay element the first input of the first comparison node is the first information input of the block, the clock input of the row number counter is the first control input of the block, the input of the pulse counter installation O is the second control input of the block connected to the input of the device About the item number counter, the output of the pulse counter bits is connected to the first information inputs of the subtracting node, the second comparison node, the switch and is the second output of the block, the transfer output of the pulse counter is the fifth output of the block, the second information input of the second comparison node is the second information input of the unit connected to the second information input of the switch, the output of the second comparison node is connected to the control input of the switch, the switch output is connected to the information input the count of the row number, the output of the first comparison node is connected to the input of the pulse driver and the input of the delay element whose output is connected to the clock input of the counter of the element number and to the input of recording the record of the row number counter whose output is connected to the clock input of the pulse counter, and the outputs of the bits the line number counter is connected to the second information input of the subtracting node whose output is connected to the second input of the first comparison node and is the first output of the block; the output of the element number counter l of a third output unit, the output pulses for- tors, connected to the first input of the AND gate, whose second input is a control input of the third unit element ,, is the output of AND fourth output block. 4. The device according to claim 1, wherein the addressing unit contains the first and second switches, the adder and the counter, the clock input of the counter is the first synchronized input of the block, the reset input of the counter is the second the synchronous input of the block connected to the control input of the first switch, the output of the counter connected to the first input of the adder, the second input of which is the first information input of the block, the first information input of the first switch is the second information input and the third output of the block, the output of the adder n It is connected to the second information input of the first switch, the first and second outputs of which are respectively the first and second outputs of the block, the control input of the second switch is the third synchronized input of the block, the first information input of the second switch is the fourth information input of the block, the third information input the first switch is the fifth information input of the unit connected to the second information input of the second switch, the third information input of which is the sixth info mation input unit, the fourth information input of the second switch is the seventh information input unit, the first and second outputs of the second switch are respectively the fourth and the fifth unit outputs fourth information input of the first switch is the third information input unit. FIG. 2 Fig.Z FIG 4 J12345678910 four 3 $ 2 I FIG. five