SU1679485A2 - Device to separate and substract the first pulse out of pulse sequence - Google Patents

Abstract

The invention relates to computing and can be used in computing device synchronization devices. The aim of the invention is to increase the reliability of operation by eliminating contests. A device for isolating and subtracting the first pulse from a sequence of pulses contains the first AND-NE 1 element, the triggers 2-6, and the second, third and fourth AND-HE elements 7, 8, 9, functionally interconnected, 2 Il.

Description

The invention relates to computing and can be used in computing device synchronization devices.

The purpose of the invention is to increase the reliability of the operation of the device by eliminating contests.

FIG. 1 shows a functional diagram of an apparatus for isolating and subtracting a first pulse from a sequence of pulses; in fig. 2 - timing charts of the device.

A device for isolating and subtracting a first pulse from a sequence of pulses comprises the first AND-NE 1 element, the first, second, third, fourth, and fifth triggers 2-6, and the second, third, and fourth IS-HE elements 7, 8, 9 connected between by itself is functional.

The device works as follows.

At the initial moment before the first pulse is fed to the bus. The input on the control bus. There is zero potential at the inverse, at the inverse output of the trigger 3 and at the direct output of the trigger 6 there are single potentials. Zero potential on the bus. The input ensures the formation of single signals at the direct outputs of the 2.4 flip-flops and at the outputs of the NAND elements 1.7. Zero potential on the bus. Reset provides the formation of single signals at the forward output of flip-flop 5 and the output of the NAND element 9. At the same time, zero signals are formed at the forward output of flip-flop 3 and inverse outputs of flip-flops 4, 5, 6. Zero signal at the forward output the trigger 3 determines the formation of a single signal at the output of the NAND element 8, which leads to the appearance of a zero signal, at the inverse output of the trigger 2. This is the state of the logic elements of the device at the initial moment of time.

At the time ti of the beginning of the pulse on the bus. The input signals on all inputs of the NANDI element 1 are single signals, and a zero signal is generated at its output. The other signals at the outputs of the logic elements at time ti remain unchanged.

At the moment t2 of the beginning of the control pulse on the bus, no changes are made at the outputs of the logic elements.

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When interfered with in the time interval between t2 and t3, the signal is interfered in chic. Resetting does not affect the output signals of the device elements.

At the moment ta of the pulse termination on the bus. An output signal is generated at the output of the NANDI element 1. This signal is fed to the input element AND-NOT 9, on the second input of which there is also a single signal. This determines the formation of a zero signal at its output. This zero signal triggers trigger 6, while a single signal is generated at its inverse output and a zero signal at the direct output that generates a single signal at the inverse output of trigger 4. The remaining signals at the outputs of the logic elements remain unchanged at time ta.

When interfering in the time interval between t.z. and t4, the interfering signal appears at the output of the AND-HE element 9 as a single short signal. Upon termination of the interference, the signal at the output of the NAND 9 element returns to its original state. The output signals of the device do not change (direct output of trigger 2 and output of the element AND-NOT 1).

At the moment tu of the start of the pulse on the bus, the input at the outputs of the AND-HE 1.7 elements and the direct output of the trigger 4 produces zero signals, and the zero signal at the output of the element AND-NOT 1 is the output signal of the device AND-NOT 9. The zero signal at the output of the element AND-NOT 7 switches the trigger 5. At the same time, a single signal is generated at its inverse output, and at the direct output - a zero signal, which confirms the single signal at the output of the AND-HE element 8 switches the trigger 3. At the same time on his direct output It is formed by a single signal, and the inverse output - zero signal. A zero signal at the forward output of flip-flop 4 confirms a single signal at the output of the NAND element 8 and switches trigger 6. At the same time, a single signal is set at its forward output, and a zero signal at the inverse output. The remaining signals at the outputs of the logic elements at the moment of step 4 remain unchanged.

When an interference occurs in the time interval between c and t /, the interference signal appears on the NAND element 7 and the direct output of flip-flop 5. After interference, the signals on the outputs of these elements return to their initial state. Weekends

the device signals do not change.

At the moment ts of the end of the pulse on the bus, the input at the outputs of the elements is NOT 1.7 and

Forward output of the trigger 4, single signals are generated. A single signal from the output of the element AND-NOT 1 is fed to the input of the element AND-HE 9, with single signals on both of the inputs of the latter, and a zero signal at the output, which in turn switches the trigger 6. At the same time, inverse A single signal is generated at the output, and a zero signal at the direct output. At the inverse output of trigger 5, a short zero pulse is received that does not affect the output signals of the device. The remaining signals at the outputs of the logic elements at time tg remain unchanged.

0When interfered with in the gap

the time between ts and t6, the interfering signal appears at the output of the AND-HE element 9 and the direct output of the trigger 5 as a short single signal. The interference signal at the right 5th output of flip-flop 5 leads to the appearance of interference at the output of the NAND element 8 as a short zero signal, which, in turn, leads to a short-term appearance of a single signal at the inverse of the flip-flop 2, However, this trigger does not switch because its unit setup input is blocked by zero input level. After

5, the termination of the interference effect, the signals at the outputs of all these elements are returned to their original state. The output signals of the device do not change. At the moment te start of the impulse on the bus

0 The input at the outputs of the AND-NE 1.7 elements and the direct output of the trigger 4 produces zero signals. The zero signal at the output of the NANDI element 1 determines the formation of the next output pulse of the device and a single signal at the output of the NAND element 9. The zero signal at the forward output of the flip-flop 4 switches the flip-flop 6, while at its forward output a single signal, and at the inverse output - de - a zero signal. The remaining signals at the outputs of the logic elements at the time te remain unchanged.

At the moment t of the termination of the control pulse on the bus. A reset at the output of the NE-NE element 7 and the direct output of the trigger 5 appears single signals. Rest. the signals at the outputs of the logic elements at time t remain unchanged.

When interfering in the time interval between t and te, the interfering signal is in- / 1 at the output of the AND-HE element 5 and direct output of the trigger 5 in the form of a short zero signal. In this case, the trigger 5 does not switch, since its input to zero is blocked by a zero signal from the inverse output of trigger 3. After the cessation of the interference, the signals at the outputs of these elements return to their original state. The output of the device is unchanged.

At the moment ta of the pulse termination, a single signal appears at the output of the T-HE 1 element. A trigger 4 appears. A single signal appears at the forward output of this trigger, and a zero signal appears at the inverse output. All inputs of the IS-NE 8 element are single signals, forming a zero signal at its output, which generates a single signal at the inverse output of trigger 2. However, trigger 2 does not switch because its input to the unit is blocked by a zero signal on the bus. The remaining signals at the outputs of the logic elements at time t8 remain unchanged.

When interference occurs between ts and tg, the interference signal appears at the output of the AND-HE element 9 and the forward output of the flip-flop 5 in the form of a short zero pulse. The zero signal from the output of the NAND 9 element switches the trigger b, a single signal is generated at the inverse output, and a zero signal at the direct output, which, in turn, generates a single signal at the inverse trigger 4 output. the interference effect, the signal at the output of the element AND-HE 9 and at the direct output of the trigger 5 returns to the initial state. In this case, the signals at the respective outputs of the flip-flops 4, b do not return to the previous state, however, this does not reflect on the output signals of the device.

At the moment tg of the beginning of the pulse on the bus. The input at the direct output of trigger 2 is formed by a zero signal, which is an output. This signal appears after the end of the pulse on the control bus. Reset with the arrival of the next pulse on the input bus. Interference does not affect it in any way. The second output signal at the output of the NANDI element 1 does not change (the pulse is subtracted from the sequence of pulses). A zero signal at the forward output of flip-flop 2 confirms a single signal at the output of the NAND element 1 and switches the flip-flop 3. At the same time, a single signal is generated at its inverse output and a zero signal at the forward output, which leads to the formation of a single signal at the output of the element IS-HE 8, which is fed to the input of the installation in unit one of the trigger 4. As a result, a zero signal is generated at the direct output of the trigger 4, which switches the trigger 6. At the same time, a single signal is generated at its direct output and output e - zero signal. The remaining signals at the outputs of the logic elements at time tg remain unchanged.

When interference occurs between tg and tio, the interference signal appears at the outputs of the AND-HE elements 7, 9 as a short zero pulse. The zero interference signal at the output of the NAND 9 element influences the input to the zero setting of trigger b, the inverse output of which has a short signal, but the trigger 6 does not switch because its input is set to 1 by a zero signal from the forward output trigger 4. The zero signal of interference at the output of the NAND 7 element switches the trigger 5. At the same time, a single signal appears at its inverse output and a zero signal appears at the forward output, which in turn determines the formation of a single signal at direct trigger output 3. In this case, the trigger 3 does not switch, since its input to zero is blocked by a zero signal from the direct output of the trigger 2. After the effect of the interference ceases, the signals at the outputs of these elements return to their initial state. The output signal of the device is not affected by the interference signal, and during this time the output pulse at the first output of the device continues and the pulse is subtracted from the sequence of pulses at the second output of the device.

At the end of the pulse on the bus, Triggers 2, 4 are switched. At the same time, single signals are generated at their direct outputs, and zero signals are generated at the inverse outputs. At the inverse of the trigger 4, the reaction of the effect of interference, which has elapsed between ts and ts, is stopped. The remaining signals at the outputs of the logic elements at time tio remain unchanged.

When interference occurs in the time interval between MO and tn, the interference signal appears at the output of element 9 as a short zero pulse that switches trigger 6. At the same time, a single signal is generated at the inverse output, and a zero signal is received at the forward output. in turn, it forms a single signal at the inverse output of the trigger 4. In this case, the trigger 4 does not switch because its input to the unit is blocked by a zero signal on the bus. Input. After the interference stops, the signal at the output of the NAND 9 element returns to its initial state. However, trigger 6 does not return to its original state and keeps a single signal at the inverse of trigger 4. This state of these elements does not affect the output signals, which remain unchanged.

At the moment tn of the start of the pulse on the bus. The output at the output of the N-NE 1 element and the direct output of the trigger 4 produces zero signals. A zero signal at the forward output of flip-flop 4 switches flip-flop 6, thereby removing the response from the effect of interference on this flip-flop. In this case, a single signal appears at its direct output, and a zero signal appears at the inverse output. The remaining signals at the outputs of the logic elements at time tn remain unchanged.

At the time ti2 of the pulse on the bus, the input at the output of the element AND-NOT 1 forms a single signal and switches the trigger 4. A single signal is generated at its forward output, and a zero signal at the inverse output, and thus the response from interference between tio and tn. The remaining signals at the outputs of the logic elements at time ti2 remain unchanged.

At the time ti3 of the start of the signal on the control bus. A zero signal is generated at the output of the NANDY element 9, which triggers trigger 6. At the same time, a single signal is generated at its inverse output, and a zero signal is generated at the forward output, which, in turn, determines the formation of a single signal at the inverse of the trigger output 4. The remaining signals at the outputs of the logic elements in the moment tis remain unchanged.

When an interference occurs in the time interval between ti3 and ti4, the interference signal appears only at the output of the AND-HE element 9 and is removed upon the termination of the interference. The output signals of the device remain unchanged.

At the time ti4 of the start of the pulse on the bus. Input signals are generated at the outputs of the AND-NE 1.7 elements and at the forward output of the trigger 4. The zero signal at the output of the AND-1 element is the output signal of the device and generates a single signal at the output of the AND element. -NOT 9. Zero

the signal at the forward output of flip-flop 4 switches over flip-flop 6. At the same time, a single signal is generated at its direct output, and a zero signal at the inverse output. The zero signal at the output of the NAND 7 element switches the trigger 5. At the same time, a single signal is generated at its inverse output, and at the direct output - a zero signal, which confirms a single signal at the output of the IS-NE element 8 and switches the trigger 3. At a single signal is generated at its direct output, and a zero signal at its inverse output. The remaining signals at the outputs of logic elements at time ti4 remain unchanged,

When an interference occurs in the time interval between ti4 and tis, the interference signals appear at the output of the NE-NE element 7 and the forward output of the trigger 5 and are removed upon termination of the interference effect. The output signals of the device do not change.

At the moment tis of the end of the impulse on pulse5. The input signals at the inputs of the AND-NE 1.7 elements and the direct output of the trigger 4 are formed by single signals. A single signal at the output of the NAND element 1 ends the formation of a pulse at the second output of the device, after which a zero signal is formed at the output of the NAND element 9. This zero signal switches the trigger 6, at the inverse output of which a single signal is generated, and output 5 zero signal. At the inverse of the trigger output 4, a short zero pulse is output that does not affect the output signals of the device. The remaining signals at the outputs of the logic elements at the moment of tis remain

0 unchanged.

At the time of the tie of the end of the impulse on the bus. A reset on the direct output of the trigger 5 and the output of the element AND-HE 9 single signals are formed. At the same time on all entrances

5 of the IS-NE 8 element turns out to be single signals, which determines the appearance of a zero signal at its output, which forms a single signal at the inverse output of flip-flop 2, However, flip-flop 2 does not switch because its unit-setting input is blocked by a zero signal level on the bus Entrance. The remaining signals at the outputs of the logic elements at the time of tie remain unchanged.

5 When interfered with the time between tie and tu, the interference signal generates zero signals at the output of the AND-HE element 9 and direct output of the trigger 5, the last of which leads to the appearance of a single signal at the output of the AND-HE element 8, which, acting on the setup input to zero of trigger 2, causes the appearance of a zero signal at its inverse output. After the cessation of interference, the signals at the outputs of all these elements return to their original state. The output signals of the device remain unchanged.

At the time ti of the start of the pulse on the bus. The input at the direct output of the trigger 2 is a zero signal, which is the output. This signal appears after the end of the pulse on the bus Reset with the arrival of the next pulse on the bus Input. The second output signal at the output of the NANDI element 1 does not change (the pulse is subtracted from the sequence of pulses). The zero signal at the forward output of flip-flop 2 switches the flip-flop 3. In this case, a single signal is generated at its inverse output, and at the forward output - a zero signal, which leads to the formation of a single signal at the output of the AND-HE element 8, which enters the installation in the unit of the trigger 4. As a result, a zero signal is generated at the direct output of the trigger 4, which switches the trigger 6. At the same time, a single signal is generated at its direct output and a zero signal at the inverse output. The remaining signals at the outputs of the logic elements at time ti remain unchanged.

At the instant of the pulse termination on the bus, the Input switches the triggers 2 and 4. At the same time, single signals are generated at their direct outputs, and at inverse outputs,

Reset

moves - zero signals. The remaining signals at the outputs of the logic elements at the time of the tie remain unchanged.

At the time of the start of the pulse on the bus tig

The input at the output of the NAND 1 element produces a zero signal. The remaining signals at the outputs of the logic elements at time tig remain unchanged.

When exposed to interference in the gap

the time between tig and t20 the interference signal does not affect the output signals of the logic elements of the device.

At the moment of the end of the pulse on the bus. The input at the output of the element AND-NOT 1 forms a single signal. The remaining signals at the outputs of the logic elements at time t20 remain unchanged. In this case, all output signals of the elements coincide with those formed at time w, i.e. Further, the operation of the device is repeated.

Due to the introduction of a new connection from the output of the AND-HE element 8 to the second input of the unit into the unit of trigger 4, the condition of the pulse fronts is completely excluded.

Claims (1)

Claims An apparatus for isolating and subtracting a first pulse from a pulse train according to the author. St. USSR N 1589273, that is, in order to increase the reliability of the device by eliminating contests, the output of the third AND-NOT element is connected to the second input of the unit to the unit of the third trigger. one 2