SU1658164A1 - Device for interfacing source and receiver of information - Google Patents

Abstract

The invention relates to computing and can be used as a device for converting and buffering data in control systems, as well as for interfacing computers with communication channels. The purpose of the invention is to expand the functionality due to the possibility of controlling the output information flow. The device contains two registers, a write character generator, a n + 1 group of record counters, two groups of buffer storage blocks, three switchboards, a group of record control units, two decoders, a counter, a trigger, and three switches. 3 il.

Description

The invention relates to computing and can be used as a device for converting and buffering data in control systems, as well as for interfacing computers with communication channels.

The purpose of the invention is to expand the functionality due to the possibility of controlling the output information flow.

FIG. 1 shows a block diagram of a device for interfacing a source and receiver of information: FIG. 2 is a block diagram of a write control unit; in fig. 3 - diagrams explaining the operation of the recording control unit.

The device of interface of the source and receiver of information contains the first register 1, the shaper of 2 recording attributes, the first counter and the group n of counters 3.1 — Z.p 1, the first buffer storage blocks, the first group of buffer storage blocks 4 1–4.

buffer storage unit and the second group of buffer storage units 5.1 - 5 n + 1, the second switch and the first group n switches 6.1 - bp 1, the third switch and the second group n switches 7.1 - 7, n + 1. the third group of switches 8.1 - 8.p + 1, group of blocks 9.1 - E.p. + 1 record management, first 10 and second 11 decoders, second counter 12, trigger 13, second register 14, first 15. fourth 16 and fifth 17 switches.

The recording control unit contains two elements 18 and 19 of the delay element And 20 and a one-shot 21,

The device works as follows.

The address-information word coming from the source into register 1 is divided therein into the address and the Address information is fed to the input of the imager of 2 recording signs, to the input of the decoder 10. to the address input of the decoder 11

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Information from the output of register 1 is supplied to the information inputs of the decoder 11 and switches 8.1 - 8.p 1. The decoder 10 when a fixed address arrives, indicating the end of the recording cycle, the device outputs a signal to clear the counters 12 and 3.1 - Z.p. t 1 and switching of the trigger 13, which controls the switching of the buffer memory blocks of 4.1 - 4.p + 1 in the write (or read) mode and the buffer storage blocks 5 1 - Б пю 1 to the read (or write) mode, depending on states of outputs For example, the initial state Trigger January 13, wherein the buffer storage units 41- 4.n i 1 are in recording mode, and the buffer storage units 5 1 - 5.p + 1 are in oezhime read. At the same time, connect the second information input connected to the output of switch 17 to the output of switch 15 to the first outputs of switches 8 1 8, n + - 1. Their information inputs are connected to the inputs of the outputs of buffer storage blocks 4.1-4. , to the outputs of the switches 51 bp 1 they connect their first information inputs, to zann, i, g counters 3 1 З.п + i to the output of communes 7.1 to 7 g, 1 to connect their second infor -1G | Zionn, t Bypass, .1, C, BS, ,, zhnye with the output of the counter 12. In they „address. incoming to Formiroyatel 2 sign of the record, the code arrives on the BLO code, “raniii in constantly. -, ar or -inserter at this address Pgl: presence of 1 in iv, iom or near the discharge of a permanent storage device, the corresponding outputs of the imaging unit 2 recording signs, signals are received to the second in the codes of the corresponding blocks 9.1-9. n 1-1 record control;, 3b), and the portions of the inputs go to the core (but information is not on (Fi (. 3o, i. Address information word after the single-circuit 21 and the delay line 18 goes to one of the inputs of the And 20 ( fig tv)

At the first and second outputs of the CUL branching blocks 9.1 - 9.p + 1 deletion, recording gates are formed by the recording, arriving at the counting inputs of the interceptors of the CCT. 3.1 - 3 n -I 1 (Fig. Zg) to the second control the inputs of the corresponding buffer storage units 4.1 - 4.p + 1, 5.1 - 5 n + 1 (Fig. Rear). At the outputs of the corresponding counters 3.1-3 p - 1, write addresses are generated.

Record addresses through switches 6.1 - 6.A + 1 are sent to address switches, and information through switches I - 8, n + 1 to inputs - outputs of buffer storage blocks 4.1 - 4, n + 1. Information is recorded in those buffer memories bpoka, on control inputs of which

formed recording gates. Thus, the received address information word is written into one or several buffer storage units.

0 In parallel with the recording of information in the buffer storage blocks 4.1 - 4.p + 1, the information of one of the buffer storage blocks 5.1 - 5.p + 1 is read as follows. The buffer storage unit, from which the information should be read, is determined by the source of information (for example, a digital computing system), which, according to the results of simulation and instrumental control

0 The function of the evil subsystems at the end of each cycle., Reading reads forms a command to fish a buffer storage unit, followed by a fixed address. The address information word, containing the 5 command to select the buffer block storage, is fed to the input of the decoder 11, the characteristic number of the buffer storage block formed by it is written to register 14 and stored there until

0 regular teams with a fixed address

The control signal from one of the registers 14 input-output of the selected bmfsrnogo storage unit connects the h & cts through the switches 17 and 15 to the output device

To read information, read signals are received from the receiver to the read input of the device. Counter 12 when

At each incoming readout signal, the readout address is formed, which through the switches 7.1-7.p + 1 post / гgche1 to the address inputs of the buffer blocks of the MININGING units 5.1-5.p + 1. The readout from the selected buffer storage unit is performed each read signal. Information from buffer storage blocks 5.1-5, item 1 goes to information inputs

0 hmmmuchator 17 and further through the switch 15 to the device output.

When a fixed address arrives at the decoder 10, indicating- .-,) about the end of the write-read cycle of the device, counters 12 and 3.1 - Z.p + 1 return to the initial state I change state of the trigger 13 by 10 Trigger 13 switches the buffer storage units j 1 - 5, n + 1 to the write mode, and the buffer storage units

4.1 - 4.n + 1 into the read mode, while the output of the switch 15 connects its first information input connected to the switch 16 to the second outputs of the switches 8.1 - 8.n-1 connected by the input-outputs of the buffer memory blocks 5.1-5.P + 1, their information inputs are connected, to the outputs of the switches 6.1-bp + 1 their information inputs are connected, connected to the outputs of the counters 3.1-Z.p + 1. The information is written and read in the same way as described

In addition to buffering the received information, the device regulates the output information flow, which allows you to select and transmit the most important current information of the transmitter and, thus, efficiently use the bandwidth and performance of the information receiver.

Claims (1)

The invention The device for pairing the source and receiver of information, containing two counters, a trigger, first to fifth switches, two buffer storage units, a write control unit, a first decoder, a register, the output of address bits of which is connected to the input of the first decoder, output which is connected to the zeroing inputs of the first and second counters, the trigger input, the first trigger output is connected to the first control input of the first switch, with the first control input of the first buffer storage unit a, with the control input of the second switch, the second trigger output is connected to the first control input of the second buffer storage unit, with the control input of the third switch, to the second control input of the first switch, whose output is the output of the device for connection to the receiver's data input , the first and second information inputs of the first switch are connected respectively to the outputs of the fourth and fifth switches, whose information inputs are connected respectively to the inputs-outputs of the first and second the first buffer storage blocks, the second control inputs of which are connected to the first output of the write control unit, the address inputs of the first and second buffer storage blocks are connected respectively to the outputs of the second and third switches, the first information inputs of which are connected to the output of the first counter, the second information inputs are with the output of the second counter, the counting input of the first counter is connected to the second output of the recording control unit, the first input of which is connected to the input of the first register and is inst the formation input of the device for connection to the information output of the source, the input of the second counter is the input of the device for connection to the output of the readout of the receiver, characterized in that 0 in order to extend the functionality due to the possibility of regulating the output information flow, a second decoder, a second register, two groups of n switches are introduced into it, 5 third group of n + 1 switches, a group of n counters, a group of n blocks of recording control, two groups of n buffer storage units, a recording feature generator, whose input is connected 0 with the output of the bits of the address of the first register and the address input of the second decoder, the first output of the recording feature generator is connected to the second input of the first recording control unit, and 5, the remaining n outputs are connected to the first inputs of the corresponding n recording control units of the group, the second inputs of which are connected to the device input for connection to the information output 0 sources, the first outputs n of the group recording control units are connected to the counting inputs of the corresponding n group counters, the outputs of which are connected to the first information inputs 5 corresponding n switches of the first and second groups, the second information inputs of which are connected to the output of the second counter, the outputs of n switches of the first and second groups are connected to the address inputs of the corresponding n buffer storage blocks of the first and second groups, respectively, the second control inputs of which are connected to the second the outputs of the corresponding n writing control blocks, the inputs-outputs of the n buffer storage blocks of the first and second groups are connected respectively to the information inputs of the fourth and fifth switches, control inputs which 0 connected to the corresponding outputs of the second register, the input of which is connected to the output of the second decoder, the information input of which is connected to the information output of the first register and 5 information inputs of n + 1 switches of the third group, the first outputs of which are connected to the corresponding inputs of the fourth switch, the second outputs of n + 1 switches of the third group are connected to the corresponding inputs The first control inputs of the third group of switches of the third group are connected to the first control inputs of the first buffer storage blocks of the first group, with the control inputs of the first switches of the first group, to the first output of the trigger, the second control inputs The n + 1 switch of the third group is connected to the first control inputs of the p buffer storage blocks of the second group, to the control inputs of the n switches of the second group, to the second output of the trigger, whose input is connected to the zero reset inputs of the group counters. Output Read input 1 flx.2 I u / xl - 0 No Out Thebes. 2 Fia.Z