SU1658151A1 - Device for exponential functions reproduction - Google Patents

Abstract

The invention relates to computing and can be used in specialized digital computers and computing devices. The purpose of the invention is to increase the speed and accuracy of the calculation of Functions, y e x The device contains a memory block of constants, four registers of the intermediate result, four normalization blocks, four adders, two registers, two coefficient calculators, four multipliers, three subtractors, a synchronization block two element OR. The synchronization block contains a decoder, a trigger, a clock generator, an element AND a shift register, a counter. The coefficient calculation blocks contain two shift registers, the AND element, the clock oscillator trigger. The normalization blocks contain two shift registers, the trigger, the clock generator, the AND element. The intermediate result registers contain the bus switch register. The device starts up on the Start signal. The number of computation cycles is determined by the code set at the corresponding input. After completing the calculations, the values ex and e x, respectively, are generated at the outputs.

Description

The invention relates to computing and can be used in specialized digital computers and computing devices.

The purpose of the invention is to increase the speed and accuracy of the calculation of the functions and x.

FIG. 1 shows the block diagram of the device in FIG. 2, the block diagram of the synchonization unit, FIG. 3, an embodiment of the coefficient calculation unit; Fig. 4 shows an embodiment of the rationing block; in fig. 5 - implementation of the register of intermediate results

The device contains input 1 for setting initial values, memory block 2, constants, intermediate result registers 3-6, normalization blocks 7 and 8, adders 9 and 10, registers 11 and 12, first and second outputs 13 and 14, coefficient calculation block 15 , block 16 normalization, multipliers 17 and 18, adder 19 block 20 normalization, subtractors 21 and 22, adder 23 multipliers 24 and 25, block 26 synchronization, input 27 of the Start signal, input 28 of the iteration number code, output 29 of the intermediate result readiness, output 30 of the sign of completion of calculations, subtractor 31 block 32 and a coefficient and OR elements 33 and 34

ABOUT

ate

00

cl

The synchronization unit 26 comprises a decoder 35, a trigger 36, a clock generator 37, an AND 38 element, a shift register 39 and a counter 40. The coefficient calculation blocks 15 and 32 contain a shift register 41, an AND 42 element, a clock generator 43, a trigger 44 and a shift register 45 The blocks 7, 8, 16 and 20 of the normalization contain the shift register 46, the trigger 47, the clock generator 48, the AND 49 element and the shift register 50. The intermediate result registers 3-6 contain the bus switch 51 and the register 52.

The operation of the device is based on the following relationships:

U2.1

USH1 (2-) U1.1 + (-1 +

) U1M +

and 0 |

(D

U2.N-1 - () U2.1 + () U2.Mgde where h is the calculation step;

, 1.2N-1;

N is the number of calculation steps;

U1.-1, U1, o. U2.-1 - given initial conditions.

The device works as follows.

In the initial state, all units of the device are set to the zero state, at input 1 to block 2 of the memory constants the constants yi, -i, yi.o are entered. U2.-1, U2, o, h, - 1,2. In block 26, synchronization on input 28 is entered the value of the code that determines the number of calculation steps fi, o

- --- when solving systems mm (1). By sigp

the input 27 starts the synchronization unit 26. By the zero clock cycle, registers 3-6 are entered into the values of yi.o, U1-1, respectively. U2, oh, U2.-1. and at the inputs of blocks 7 and 8, subtractors 21 and 22, adders 19 and 23, the constants h, -1,2 are set for the entire calculation period. According to the formula (1), in the first cycle in block 32 of calculating the coefficient ai, block 15 of calculating the coefficient /, the values of the coefficients a and / U are calculated, the second cycle in the blocks 7 and 8 of the normalization form the values of h / a and h //, and on the third in the subtractors 21 and 22, the values (2-у2, о / Оо) and (2 -yi.o // 3o) are formed; in the adders 19 and 23, the values (- 1 + corner / Oo) and (- 1 + yi.o // 30). in the fourth cycle, multipliers 17 and 24 calculate the values (2-у2, о / Оо) and (-1+ + 2 У2.0 / Д) у2, о, and on multipliers 18 and 25 the values ( -1+ y2, o / Oo) yi, -i and (-1 + U1.0 // Zo) y2, -1, according to the fifth tact, the expressions p / ob + are formed in adders 9 and 10

+ (2-u2.0 / Oo) U1.0 + (-1+ U2.0 / “o) U1.-1 And (2-yi.O / A))

У2, о + (-1+ У1,) у2, -1, by the sixth cycle in

subtractor 31 forms -h // 30 + (2-yi, o /

//30) 2.2.++ (-1+ У1.) У2, -1 in the seventh cycle

information from registers 3 and 5 is rewritten into registers 4 and 6, respectively, and in registers 11 and 12 it is recorded from the outputs of adders 9 and 10; in the eighth cycle, information from registers 11 and 12 is rewritten into registers 3 and 5, respectively,

Thus, after the first cycle of transformations, yi, -i are formed at the first output 13, yi, i - at the output of the register 3, U1, o at the output of the register 4, y2, -1 - at the second output 14, у2,1 - by the output of register 5, wah. o at the output of register 6. The cycles are repeated in the same sequence until the signals from outputs 29 and 30 allow retrieving information from the output of the device,

Claims (1)

Invention Formula A device for reproducing functions and containing first, second, third and fourth adders, first and second multipliers, first register, first and second OR elements, first, second, third and fourth intermediate result registers and a synchronization unit, characterized in that in order to increase speed and accuracy of calculation, it contains the first and second blocks of the coefficient calculation, the first, second, third and fourth blocks of the valuation, the third and fourth multipliers, the first, second and third subtractors, the second register, the output of the signal. The zero clock of the synchronization unit is connected to the first inputs of the first and second OR elements and to the first inputs of the switching control of the first, second, third and the fourth intermediate result registers, the output of the signal The first clock of the synchronization unit is connected to the control inputs of the first and second coefficient calculation blocks and to the second inputs of the switching control of the first, second, third and fourth registers of the intermediate result, the signal output. The second clock of the synchronization block is connected to the control the inputs of the first, second, third and fourth blocks of the normalization, the output of the signal The third clock of the synchronization block is connected to the control inputs of the first and second first and second adders, output The fourth clock cycle of the synchronization unit is connected to the control inputs of the first, second, third, and fourth multipliers, the signal output. The fifth clock cycle of the synchronization unit is connected to the control inputs of the third and fourth adders, the output of the signal The sixth cycle of the synchronization unit is connected to the control input of the third subtractor. the output of which is connected to the information input of the second register, the control input of which is connected to the control input of the first register, the control inputs for recording the second and fourth registers of the intermediate result and the output of the first OR element, the second input of which is connected to the output of the signal of the Seventh clock cycle of the synchronization unit, signal output The eighth clock of the synchronization block is connected to the second input of the second OR element, the output of which is connected to the recording control inputs of the first and third intermediate registers As a result, the output of the first register is connected to the first information output of the device and the first information input of the first register of the intermediate result, the output of which is connected to the first information inputs of the first multiplier and the fourth normalization unit, to the information input of the second coefficient calculation unit and the country of the intermediate result, the output of which is connected to the first information INPUT of the SECOND MULTIPLE, OUT which is connected to the first information input of the third adder, the output of which is connected to the information input of the first register, the output of the second register is connected to the second information output of the device and to the first information input of the third register of the intermediate result, the output of which is connected to the information input of the first coefficient calculation unit, with the first information inputs of the second rating unit, the third multiplier and the fourth register of the intermediate result, the output of which is connected with the first information input of the fourth multiplier, the output of which is connected to the first information input of the fourth adder, the output of which is connected to the input of the decremented third subtractor, the input of which is decremented is connected to the output of the third valuation unit, the first information input of which is connected to the output of the second coefficient calculation unit and with the second information input of the fourth rationing unit, the output of which is connected to the first information input of the second adder and the input of the subtracable second subtractor, the output of which is connected to the second information input of the third multiplier, the output of which is connected to 0 the second information input of the fourth adder, the second information input of the fourth multiplier is connected to the output of the second adder, the second information input of which is connected to the input 5 constants Minus one device and with the first information input of the first adder, the output of which is connected to the second information input of the second multiplier, the second information input of the first 0 the adder is connected to the input of the readable first subtractor and with the output of the second valuation unit, the second information input of which is connected to the output of the first coefficient calculation unit and with 5 with the first input of the first valuation unit, the output of which is connected to the second information input of the third adder, the third information input of which is connected to the output of the first multiplier, the second information input of which is connected to the output of the first subtractor, the decrement pass of which is connected to the input of the decremented second subtractor and to the input constants two devices, second 5, the information input of the first valuation unit is connected to the input of the task assignment of the computing step of the device and with the second information input of the third valuation unit, the second information inputs 0 of the first, second, third and fourth registers of the intermediate result are connected to the first, second, third and fourth inputs of the initial values of the device, respectively, the signal input 5 The start of the synchronization block is the device start input, the input of the number of cycles of the synchronization block is input of the device number of iterations code, the first and second control outputs of the block The sync 0s are the outputs of the readiness sign of the intermediate result and the sign of the completion of the device calculations. I lrai " be 3 FIG. 2 Fiz.Z BN 7.8.16,20 From Я6 Record OTB Go47 " 0t5ig BU26 57 61/26 P mp. ot - 5ff Z6 W f / 77.p. Yas Zl, 5.5 52 t