SU1654974A1 - Pulse-duration-to-number converter - Google Patents

Abstract

The invention relates to information technology and is intended to convert signals into a digital code. The purpose of the invention is to increase the reliability of the output information. The goal is achieved by the fact that a pulse former 7, a second OR OR NOT 5 element, a pulse former 7, a D-flip-flop 8, an AND 9 and D element are entered into a pulse width converter into a digital code containing a clock bus 1, the first element OR NOT 2. - trkgger 10. The introduction of these elements allows to eliminate the input signal bounce and bring the device to its initial state at the moment when there are no pulses along the input bus. 1 il.

Description

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The invention relates to information technology and is intended to convert signals into a digital code. The purpose of the invention is to increase the reliability of the output information by separating the pulses by duration, eliminating the influence of bounce and bringing the device to the initial state at the moment when there are no pulses on the input bus.

The drawing shows the functional diagram of the Converter.

The pulse width to digital converter contains a clock bus 1, an element of OR-NOT 2, a counter 3, an output bus of 4, an element of OR-NOT 5, an input bus 6, a driver 7, a D-flip-flop 8, an element of AND 9, a D-flip-flop 10 bus 11 installation in "O.

The Converter operates as follows.

The reference frequency signals are constantly present at the clock input 1 of the converter. The initial setup bus 11 is on the rising edge of the signal. Reset the first D-flip-flop 10 is set if there is no signal at input 6 of the converter and, having passed through AND 9, sets the first 10 and the second 8 D-triggers to zero. If the input pulse is present at the moment of the arrival of the signal "Reset at input 6 of the converter, then the logical" 1 from the output of the first D-flip-flop 10 does not pass through the element AND 9 until the pulse on the input bus 6 runs out. This excludes the possibility convert part of the input pulse to the code. The input chain of the imaging unit 7 and the second element OR-NOT 5 is designed to protect against the noise of the input pulses. Shaper 7 operates as a restartable one-shot, and the duration of the pulses generated by it is selected based on the frequency of the expected bounce so as to exceed the maximum bounce period. At the output of the second element OR-NOT 5, the input pulses are converted to inverted and without chatter. This eliminates the possibility of converting the chattering pulse duration into a code and the possibility of a skip due to this main pulse.

When a single pulse arrives at input 6, on condition that the converter is in standby mode, i.e., the signal "Reset has already zeroed counter 3 and both D-flip-flops 8 and 10, begins to complement counter 3, since at its input zeroing the logical “О and logical“ О on the first, third and fourth inputs of the first element OR NOT 2 allow the clock 3 to pass through the counting input to the counting input 3. At the end of the input pulse, the positive edge at the output of the second element OR NOT 5 is passed to the second D-trigger 8 is written logical "one,

which prohibits the passage of clock pulses through the first element OR-NOT 2 until the signal “Reset on the initial setup bus 11” appears, indicating that the device processing information about the duration of the input pulses of the device is ready to receive further information. The signal "Reset Converter is reset to its original state.

The transfer input of counter 3 is used to stop it in the augmented (single) state, i.e., in the case where the duration of the input pulse exceeds the filling time of counter 3, the logical "1

at the output of the transfer, it prohibits the passage of clock pulses through the first element OR NONE 2, stopping the counter 3 in one state. Thus, the single state of the counter 3 indicates the arrival of unnecessary long pulses,

0 since the required range of variation in the duration of the received input pulses is determined by selecting the clock frequency and the volume of the counter 3.

 The proposed construction of a transducer of the pulse duration to a digital code eliminates the possibility of incorrectly determining the pulse duration in the case when the pulse duration exceeds the filling of the counter 3, i.e., stopping

0 of the counter 3 through the first element OR-NOT 2 in the logical "1" state at its outputs means that the duration of the input pulse exceeds the upper threshold of the range of measured pulses. In addition, permission to fill the counter 3 is made only in the absence of a pulse on the input bus, which eliminates the conversion to the code of the part of the input pulse. The proposed converter also has a chatter protection, which excludes the possibility of a pulse being skipped due to the influence of chatter. In addition, in the proposed version of the converter construction there are no restrictions on the duration of the signal "Reset.

Claims (1)

Invention Formula ° Pulse width to digital converter containing the first element OR-NOT, the first input of which is the input bus, the second element OR-NOT, the first input of which is the bus 0 clock pulses, and the output is connected to the clock input of the pulse counter, the outputs of which are the output bus, characterized in that, in order to increase the reliability of the conversion, a driver, two т triggers, and the first input element are combined with C the input of the first D-flip-flop, the second input of the second element OR-NOT and connected to the output of the first element OR-NOT, the second input of which is connected to the output of the former, the input 1654974 56 which is an input bus, the second / input is combined with the input of the first the input element And is combined with the input of the set-D-flip-flop and is connected to the output of the element in the “About the pulse counter and the And connection, the output of the first Ј-trigger is connected to to the output of the second D-flip-flop, the D-input of which is the third input of the second element OR NOT, The ply is a tire whose corresponding fourth input is connected to the output the capacity, the C input is set by the bus in the “O”, pulse counter overflow.