SU1649667A1 - Decoder for adaptive delta-modulation communication system - Google Patents

Abstract

This invention relates to communication and computing technology. Its use in the construction of digital communication systems makes it possible to improve the decoding accuracy in terms of packet error in the communication channel. The decoder contains an amplitude-pulse modulator 1, an integrator 2, a low-pass filter 3, a selector of 4 packs of symbols, a shift register 7 and a smoothing filter 8. By introducing selectors 5, 6 packs of symbols, a smoothing filter 9, a sampling and storage unit 10 and a switch 11, in the decoder, the integrator 2 is zeroed out when an error packet appears (with a duration longer than the maximum allowed) and connected for the duration of this packet to the modulator 1 stored by the sampling and storage unit 10. This reduces the duration and intensity of transients. 1 il. (L

Description

The invention relates to communication technology and computer technology and can be used in the construction of digital communication systems.

The purpose of the invention is to increase the accuracy of decoding in the conditions of packet errors in the communication channel.

The drawing shows a block diagram of a decoder.

The decoder contains an amplitude-pulse modulator 1, integrator 2, lowpass filter 3 (low-pass filter), the first and third selectors 4-6 packets of characters, shift register 7, the first 8 and second 9 smoothing filters, block 10 selection and storage and switch 11. The drawing shows the information and clock inputs 12, 13.

Selectors 4-6 packs of characters are made each on a shift register, the direct and inverse outputs of which are connected to the first and second inputs of the element of equivalence (equivalence). The first and second selectors 4, 5 are the same.

Block 10 sampling and storage can be implemented, for example, on an operational amplifier with a capacitor at the input.

The decoder is based on the following.

In decoders with one selector of symbol bursts, when a digital signal arrives at its input and is exposed to a digital packet error in the form of a long sequence of unipolar (e.g., negative) pulses, after a while the voltage at the integrator's output will become minimally possible (negative). In addition, in accordance with the adaptation of the quantization step adaptation algorithm, after each m-valued overlapping combination of the same name symbols received at the input of the symbol pack selector, a positive impulse will appear at the output of this selector. The number w is usually 2; -5, depending on the clock speed of the encoder. Successive positive pulses from the output of the symbol pack selector charge the smoothing filter to the maximum possible value, which corresponds to the maximum possible quantization step. Thus, after the termination of the error packet in the input digital signal, the trajectory of the output signal will begin with a negative saturation level, and the quantization step will be maximally possible. Normalization of the operation of such a decoder occurs in accordance with the time constants of the smoothing IQ filter and integrator.

Obviously, in order to minimize the duration of the transient processes that arise in this case, it is necessary to establish the most probable values of the voltages at the outputs of the integrator (approximating output voltage) and a smoothing filter (quantization step) by the time the error packet ends. Since the length of the error packet is sufficiently large, there is no correlation between the signal samples before the action, the packet, and immediately after it. Therefore, the most likely 25 value of the approximation voltage at the output of the integrator is ”0.

I

The quantization step control signal in a syllabically adapted decoder changes much slower than the speech signal itself. Therefore, during a period of time equal to the duration of exposure pas _{March 5} ketnoy errors (assuming that the length of the package ,, less than the duration of the syllable), the quantization step value (voltage at the smoothing filter output) is changed in small pre _d d matters in the absence of failures in digital. howling sequence.

Therefore, the most likely quantization step after the end of the error packet is equal to that which was before it began.

These principles are implemented in the decoder in question.

If a digital signal arrives at decoder input 12, which is not distorted by digital packet errors, then it goes to integrator 2, being modulated in an amplitude-pulse modulator (AIM) 1. A signal is generated at the second input of AIM 1, which is generated by the first selector of symbol packets and the first smoothing filter 8 (the output of switch 11 is connected in this case with its first information input) ... The operation of de5 encoder in this case is carried out in the same way as in the prototype device.

The presence of a packet digital error in the input information signal 'is determined using the third selector of 6 packets of symbols tuned to the threshold (maximum possible in an undistorted DM signal) number of consecutive unipolar pulses of n. The presence of a burst in the digital sequence with the number of characters greater than and leads to the appearance at the output of the third selector of 6 packets of symbols of the level of logical G *.

Error detection in the digital sequence occurs with a delay of η clock intervals of the digital signal, the action of which leads to a significant change in the quantization step at the output of the first smoothing filter 8. Therefore}? to correctly fix the quantization step present at the second input of AIM 1 at the time of the appearance of a packet error in the digital information signal, a signal identical to the one arriving at the second input of AIM 1 but delayed by η clock intervals is supplied to the information * input of block 10. This signal is generated from the information sequence delayed by η clocks in the shift register 7, using the second selector 5 packs of characters and the second smoothing filter 9, which are completely identical to the first selector 4 packs of characters and the first smoothing filter 8, respectively.

A signal with a logic level of 1 ”at the output of the third selector 6 packets of symbols is zero for the integrator 2 and control for the switch 11 and the block 10 selection and storage. Integrator 2 when logic level 1 is zeroed at its input is discharged, and the voltage at its output is kept at 0 all the time, while logic 1 is present at its zeroing input.

Switch 11 connects its output to the second information input and remains in this position all the time, while at its control input there is a logical level ”1. Block 10 sampling and storage captures (stores) the magnitude of the voltage on

1649567 ⁰ its information input, numerically equal to the quantization step before the start of the packet error, and stores it until a logical 1 '' level is present at the control input. The fixed voltage value through switch 11 and the first smoothing filter 8 is fixed (θ is supplied to the second input of AMI 1. Provided that the direct current transfer coefficient of the first smoothing filter 8 is unity, after a while the quantization step is fixed at its output15, fixed in block 10.

Thus, by the time the packet of digital errors ends, the second input of AIM 1 will have the required quantization step value 20, and the required approximation value at the output of the integrator 2.,

At the end of the error packet in the digital information signal at the 25th output of the third selector 6 packs of symbols, the logical level 0 again appears, the input of which to the control inputs of switch 11, block 10 and reset input 30 of integrator 2 leads to the connection of the output of switch 11 with its first information input, respectively , transferring block 10 again to the mode of selecting information and disabling 35 reset of the integrator 2. The operation of the decoder of the communication system with adaptive delta modulation is resumed from the required initial conditions.

Using this' decoder can reduce the duration and intensity of transients, thereby reducing the distortion of the restored signal. Thus, the use of a decoder in the communication system 45 with an adaptive DM operating on digital channels with packet errors will improve the quality of message reception.

Claims (1)

50 claims A decoder for an adaptive delta-modulation communication system containing a first selector of symbol bursts, 55 whose information input is the decoder information input, the clock input is combined with the shift register clock input and is the decoder clock input, first smoothing filter, pulse-amplitude modulator, the output of which is connected to the information input of the integrator, the output of which through the low-pass filter is connected to the output of the decoder, characterized in that, in order to increase the accuracy of decoding in conditions of packet errors in the communication channel, a second symbol pack selector and a smoothing filter, a switch, a sampling and storage unit and a third symbol pack selector, the information input of which is combined with the first input of the pulse-amplitude modulator, the information input of the Shift register and connected, are inserted into the decoder to the information input of the decoder, the clock inputs of the second and I '-' "third symbol pack selectors' are connected to the clock input of the decoder, the output of the first packet selector of 5 characters is connected to the first information input of the switch, the output of which through the first smoothing filter is connected to the second input of the amplitude-pulse modulator 10, the output of the shift register is connected to the information input of the second selector symbol packs, the output of the second smoothing filter is connected to the information input of the sampling and storage unit 15, the output of which is connected with the second information input of the switch, the output of the third selector of packets of characters under the keys to the control inputs of the block ί 20 sampling and storage and switch and input bnuleniya integrator.