SU1647633A2 - Device for digital magnetic recording - Google Patents

Abstract

The invention relates to the accumulation of information, namely to a magnetic recording technique. The purpose of the invention is to improve the accuracy of digital magnetic recording. The device for digital magnetic recording contains a master oscillator 4, a trigger 1, three elements AND 3, 5, 12, a recording unit 2, two delay elements 6.7, a static register 8, a shift register 9, a memory block 10, a counter 13, a multiplexer 14. New is the introduction of an additional static register 15. 1 Il.

Description

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The invention relates to a technique of magnetic recording and is an improvement of the device according to the author, St. No. 1509992.

The aim of the invention is to improve the accuracy.

The drawing shows a device for digital magnetic recording (for example, for p 2 or p 4).

The device contains a trigger 1 connected to the input with the output of the first element 3, connected by the first input to the first output of the master oscillator 4, the second element 5, the first and second elements 6 and 7 of the delay, the static register 8, the shift register 9 and the memory block 10 . The second output of the generator 4 is connected to the first input of the second element 5, connected by the output via the first delay element 6 to the sync-synchronizing input of the static register 8. The second delay element 7 is connected by an output to the clock input of the shift register 9 connected by the information input to the input bus 11 connected to the first address input of the memory unit 10. The latter is connected by the first group of address inputs to the outputs of the shift register 9, connected by the second group of address inputs to the outputs of the static register 8, connected by the outputs and additional outputs respectively to the information inputs of the static register 8 and to the address inputs of the third group of the memory block 10 itself.

The device also contains a third element And 12 connected by an output to the second input of the second element And 5, a counter 13 connected by an output to the second address input of the memory unit 10 and connected by an input to the second output of the master oscillator 4 connected to the input of the second delay element 7, multiplexer 14, connected by an output to the second input of the first element and an additional static register 15 connected by outputs to the address inputs of the fourth group of the memory block 10. In this case, the information inputs of the additional static register 15 are combined with the address inputs of the third group of the memory block 10, and the synchronization input of the additional static register 15 is combined with the synchronization input of the static register 8, the outputs of which are connected to the channel inputs of the multiplexer 14, connected by other outputs of the counter 13 connected to the inputs of the third element And 12. The device operates as follows.

JQ Zero binary signal from the first bit of register 8 is fed to recording unit 2 through multiplexer 14, first AND 3 element and trigger 1. Digital information binary signal is recorded for the first bit of registers 9 with information shift in the remaining -, bit according to the clock signal of the master oscillator 4. The clock signal of the oscillator 4 changes the state of the counter 3, which ensures that the signal from the second bit of the register 8 enters the recording unit 2 through the multiplexer 14. As a result, the permission to record the output 5 is prepared. combine tion of binary symbols.

The counter 13 enters a state in which the zero character is read from the third bit of register 8 in block 2 of the record. Then 0, the counter 13 is transferred to the state at which the zero character is read from the fourth bit of the register 8 into the block 2 records. When the input information from the bus 11 is equal to four, the unit states of the first two bits of the counter 14 open the second element AND 5 to pass the clock signal from the generator 4 to the clock, the inputs 0 of the registers 8 and 15,

In memory block 10, information of an even number of matrices of the Latin square of each pair is stored. At the synchronization input of registers 8 and 15 5, a record of characterized two-argument functions from even-numbered matrices is provided. Next, the work takes place similarly to that described with alternating even and odd numbers and working matrixes.

Claims (1)

The invention The device for digital magnetic recording of the author. St. By 1509992, due to the fact that, in order to improve accuracy, an additional static register was entered into it, the synchronizing course of which is connected to the synchronizing 51647633 the input of the static register, and the inputs of the memory unit, the fourth grouping voles - with the additional address inputs of which are connected to the outputs of the memory unit, which the yen with the outputs of the additional are connected to the third group of address registers.