SU1647509A1 - Time intervals of pulse sequences meter - Google Patents

Abstract

The invention relates to a pulse technique and can be used to measure time intervals. The aim of the invention is to improve the measurement accuracy. The device contains drivers 1 and 2. bus 3, pulse counter 7, bus 9, memory blocks 14 and 21, bus 17. Introduction to the device of the trigger 4, elements 5, 6, 12 and 19 of the delay element OR 8, two generators 10, 15 linearly varying voltages, two formers 11 and 18, two analog-to-digital converters 13 and 20, and element 16, with the emergence of new connections between all elements of the meter, allows us to achieve the goal of the invention. 2 Il.

Description

The invention relates to a pulse technique.

The aim of the invention is to improve the measurement accuracy.

Figure 1 shows the functional diagram of the meter; figure 2 - timing charts of his work.

The input of the imaging unit 1 pulses on the leading edge is connected to the input of the imaging unit 2 pulses on the falling edge and to the input bus 3, and the output - to the second input of the trigger 4 and the input of the delay element 5. The output of the imaging unit 2 is connected to the input of the delay element 6, with the counting input of the pulse counter 7 and with the first input of the element OR 8, the second input of which is connected to the installation bus 9 and the input of the zero setting of the pulse counter 7, and the output to the first input of the trigger 4. Input (starting of the generator 10 linearly varying voltage is connected to the second output of the trigger 4. reset input — with the output of the reset driver 11, connected to its input with the output of the delay element 12, and output to the input of the analog-digital converter 13 connected Its output to the information input of the memory block 14. The starting input of the generator 15 linearly varying voltage is connected to the output of the element 16, connected by its first and second inputs to the first output of the trigger 4 and the installation bus 17, respectively, the reset input to the output of the raiser 18 reset pulses connected by their input to the output of delay element 19, and output to the input of an analog-to-digital converter 20 connected by its output to the information input of memory block 21. The output of the delay element 5 is connected to the input of the delay element 19 and the access input of the memory unit 21. The output of the delay element 6 is connected to the access input of the memory unit 14 and the input of the delay element 12. The output of the counter 7 pulses

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four

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connected to the address inputs of memory blocks 14 and 21.

The meter works as follows:

Before starting the measurements, a short start pulse (Fig. 2a) arrives from the bus 9, which zeroes the counter 7 (Fig. 2c) and, passing through the OR element 8, enters the first input of the trigger 4, the first output of the trigger 4 sets the signal corresponding to logical 1 (fig.2zh), and on the second - the signal corresponding to the logical O (fig.2z). Simultaneously with the arrival of a trigger pulse, a signal corresponding to a logical 1 (Fig. 2b) appears on bus 17, under the action of which an element 16 is opened on the second terminal. At the output of element 16, a signal appears corresponding to logical 1 (fig. 2i), under the action of which the generator 15 is started. The voltage at the output of generator 15 begins to increase linearly (fig. 2p).

The measured pulse sequence from bus 3 (FIG. 2b) is fed to the inputs of drivers 1 and 2. Shaper 1 generates short pulses at the times corresponding to the leading edges of the pulses of the input sequence (Fig. Shaper 2 - at times / corresponding fronts these pulses (fig. 2d). The pulses from the output of the former 2 are fed to the counting input of counter 7, the content of the latter with each pulse from the output of the former 2 is increased by one (FIG. 2c). The contents of the counter 7, which is the address ohm respective block rows 14 and 21 ,, the output from the counter 7 is supplied to the address inputs of the blocks 14 and 21.

On the first impulse from the output of the imaging unit 1, the trigger 4 is transferred, the signal corresponding to the logical O (FIG. 2g) appears at its first output and at the output of the element M 16, and the signal corresponding to the logical 1 appears at the second (FIG. ). Under the action of the signal from the output of the element 16, the voltage at the output of the generator 15 ceases to change (Fig. 2p). and the signal from the second output of the trigger 4 starts the generator 10, and the voltage at its output begins to increase linearly (FIG. 2),

The voltages from the outputs of the generators 10 and 15 are digitized by the converters 13 and 20, respectively, and the result of the conversion is fed to the information inputs of the memory blocks 14 and 21, respectively.

Pulses from the output of shaper 1 through delay element 5, having a slight delay, exceeding the transient process time in converters

13 and 20, are fed to the input of the inversion of the block 21 and to the input of the element 19 (Fig. 2k). The zero line of block 21, which currently corresponds to the zero content of counter 7, is recorded from the output of the transducer body 20, arriving at the information input of block 21. The pulse from the output of delay element 5, the passage through element 19, which has a slight delay sufficient to record the number from the output of the preconductor (13) 20 to the block (14) 21. goes to the gathering of the former 18. The latter forms a pulse (fig.2l), under the action of which the voltage at the output of the generator 15 drops to zero level (fig.2r).

0 At the moment of termination of the first pulse of the input sequence (Fig. 2b), a pulse appears at the output of shaper 2 (Fig. 2e), which is fed to the counting input of the pulse counter 7 and through element 8

5 (FIG. 2e) to the first input of the trigger 4. The contents of the counter 7 become equal to one. The trigger 4 is transferred, the signals corresponding to logical 1 appear on its first output and on the output of element 16 (fig.2h, i), and on the second, the signal corresponding to logical o (fig.2z). The voltage at the output of the generator 10 ceases to change (Fig. 2p), and the generator 15 starts up again, and the voltage at its height begins to increase linearly (Fig. 2p).

The pulse from the output of the imaging unit 2 through the delay element 6, identical to the delay element 5, is fed to the input of the access of the memory block 14 and to the input of the delay element 12 (Fig. 2m). The first line of block 14. corresponding to the current content of the counter 7. records the number from the output of the converter 13, corresponding to the duration of the first pulse of the input sequence 5 and arriving at the information input of the block 14. The pulse from the output of delay element 6, passing through delay element 12 identical delay element 19 arrives at

0 the input of the former 11. The latter forms a pulse (fig.2n), under the action of which the voltage at the output of the generator 10 drops to zero.

Under the action of the second pulse from the output of the shaper 1, which appears at the moment of the end of the first interpulse interval, the trigger 4 is again shifted (Fig. 2h, h). The voltage at the output of the generator 15 ceases to change (Fig. 2p), and the generator 10 is restarted.

and the voltage on its output begins to increase linearly. The second pulse from the output of the imaging unit 1 through the delay element 5 is fed to the input of the circulation 5 of the 21 memory, and the first line of this block, which currently corresponds to the contents of the pulse counter 7, records the number from the output of the converter 20, corresponding to the duration of the first interpulse interval and input unit 21. The pulse from the output of the delay element 5, the passage through the element 19, enters the input of the imaging unit 18. The latter again forms a pulse (FIG, 2L), under the action of which the output voltage f generator 15 falls to zero level (Fig. 2p).

At the end of the second pulse of the input sequence, the driver 2 again forms a short pulse, under the action of which the contents of counter 7 increase by one and become two.

Then the cycle repeats.

At the end of the measurement, a potential corresponding to logical 0 (fig.2b) appears on bus 17, element 16 closes at the second input, a signal corresponding to logical 0 (fig.2i) appears at its output and the start input of generator 15, and the voltage at the output of the generator 15 ceases to vary. As a result, by the end of the input sequence, block 14 contains the digital code for the duration of each pulse of the input sequence, and block 21 is the digital code for the duration of each interpulse interval, the line number of block 14 corresponds to the pulse number, and the line number of block 21 is the number of interpulse interval.

Claims (1)

Invention Formula Measuring the time intervals of pulse sequences, containing a pulse shaper on the leading edge, pulse shaper on the falling edge, a pulse counter and two memory blocks, in the cator, the inputs of the pulse drivers are connected to the input bus, the zero setting input the pulses are connected to the first installation bus, and the output is connected to the address input of the first memory block, characterized in that, in order to improve the measurement accuracy, a trigger, elements OR are entered into it And And, two generators of linearly varying voltage, two analog-digital converters, two formers of dump pulses and four delay elements, the output of the driver of pulses for the falling edge is connected to the input of the second delay element and to the first input of the OR element connected by the second input to the first installation bus, and the output to the first input of the triter, the second to the second the installation bus, and the output with the start input of the first generator of linearly varying voltage, the reset input of which is connected to the output of the first reset pulse generator connected with its input to the output of the third delay element, and the output of the first analog-digital converter, the output of the pulse former on the leading edge is connected to the second input trigger and with the input of the first delay element, the output of which is connected to the input of the third delay element and with the access input of the first memory block, the second input of the trigger is connected to the start input of the second generator of linearly varying voltage, the reset input of which is connected to the output of the second reset pulse generator connected by its input with the output of the fourth delay element, and the output - with the input of the second analog-to-digital converter, the outputs of the first and second analog-digital converters are connected to the inputs of the first and second memory blocks, respectively, the address inputs which are combined, and the output of the second delay element is connected to the input of the fourth delay element and the access output of the second memory block. Editor T.Zubkova Order 1649