SU1644170A1 - Electric drive controller - Google Patents

Abstract

The invention relates to electrical engineering and can be used for reversing control of a DC motor. The aim of the invention is to increase the reliability of operation by eliminating the through currents. The device contains two counters 1 and 2 pulses, trigger 3, two elements AND 4 and 5, element OR 6, three elements NOT 7–9, four keys 10–13, block 14 specifying codes, register 15 of the delay code, generator 16 pulses, bridge inverter 17. 3 Il.

Description

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The invention relates to the field of electrical engineering and can be used for reversing control of a DC motor in automatic control systems.

The aim of the invention is to increase the reliability of operation by eliminating the through currents during the formation of PWM signals of different durations.

Figure 1 shows the block diagram of the device; 2 and 3 are timing diagrams explaining its operation.

The device contains the first 1 and second 2 pulse counters, the trigger 3, the first 4 and the second 5 elements AND, the element OR 6, the first 7, the second 8 and the third 9 elements NOT, the first 10, the second 11, the third 12 and the fourth 13 keys , block 14 task codes, register 15 delay code, the generator of 1 b pulses, bridge inverter 17.

The device works as follows.

Due to the fact that the processes occurring in the device are periodic, the description of its operation is performed from the time when the output O of the inverse pulse counter transfer (reverse) appears signal O, which is inverted by the element HE 8 (FIG. 3b) and arrives on inputs of preliminary record of counters of 1 and 2 impulses (reversive). In the pulse counter 1, a code is input from the output of the code setting unit 14, and a code is recorded in the pulse counter 2. coming from the output of register 15 delay code. In the delay code register 15, recording is made from the code setting unit 14 along the delay code setting chains.

The frequency of recording information in the register 15 of the delay code is determined by the operating conditions of the bridge inverter 17 and in the general case can be one-time. xIn addition, the signal from the output of the second NOT 8 element enters the input of trigger 3. On the falling edge of the input signal, trigger 3 changes its state to the opposite (Fig. 3a). The high potential at the output of the trigger 3 (single state) provides the summation mode of the first counter 1. At the same time, the pulses coming from the generator of 16 pulses (Fig. 2a) to the counting input of the first counter of 1 pulses start to be added to the code recorded in the counter. The summation of pulses with a code occurs until an O signal appears at the output of the transfer P of the first counter 1 of pulses. By this signal the code is recorded into the first counter 1 of pulses and the trigger state changes

3, which leads to a change in the counting direction in the first pulse counter 1. The subtraction of the pulses of the generator 16 pulses from the code recorded in the counter occurs

until the appearance of the signal O at the transfer output P, then the process is repeated. As a result of the work described, pulses are generated at the output of the second element HE 8 (FIG. 3b), and at the output of trigger 3 (FIG. 3b) a PWM signal, the duty cycle of which depends on the input code. In parallel with the work described, the code is recorded in the counter 2 pulses. Consider his work, as a result of recording information content

The second counter 2 is not zero and at its transfer output P a high potential appears (Fig. 3g), which opens the second element I 5 at the first input. Pulses from the output of the generator 16 pulses start

through the second element And 5 to arrive at the counting input of the second counter 2 pulses. The latter works in subtraction mode. The pulses from the generator 16 pulses are subtracted from the code written to the counter before the occurrence of the signal O at its transfer output P (Fig. 2d), the second element AND 5 closing on the first input. The described cycle is repeated when the next pulse arrives from the output of the second

element HE 8 (figure 2 b and d). As a result of the approved operation, at the transfer output P of the second counter 2 pulses, delay signals are generated, the duration of which is given by the value of the delay code.

The signals at the output of the second counter 2 pulses are tied to the edges of the pulses at the output of the first counter 1 pulses and are ahead of them by the pulse duration of the second element HE 8 (fig.2b. C and d), i.e.

the delay signals are connected to the PWM signal.

The PWM signal from the output of the trigger 3 is fed to the first inputs of the first element AND 4 and the element OR 6. The delay signal goes to the second input of the element OR b and through the third element NOT 9 to the second input of the first element AND 4.

At the output of the latter, a signal is formed, the duration is less than the PWM signal by the delay value (Fig. 3v, guide). At the output of the element OR 6, a signal is formed that is longer than the PWM signal by the value of the delay signal (Fig. 3d, g, e) .

Thus, at the output of the element OR 6 and at the output of the first element AND 4 (FIG. 3), PWM signals are formed, between which a delay e is formed, which allows to eliminate through-currents in the bridge inverter for any duration of the PWM signal.

The delay time e is set by the code setting units 14 and is selected from the transient condition in the bridge inverter.

The sign of the direction of rotation from the output of the code setting unit 14 determines through which keys the PWM signals are sent to the bridge inverter. If it is equal to 1, then the third 12 and fourth 13 keys are open, if O, then the first 10 and second 11 keys.

Thus, the proposed device has an increased reliability of operation, since it allows the generation of a PWM signal of any duration and the elimination of through currents.

Invention Formula

The device for controlling the electric drive, containing the first pulse counter, a trigger, two NOT elements, four keys, a code setting block, a pulse generator, a bridge inverter, an OR element and two AND elements, the first group of information outputs of the code setting block, respectively, connected to the information inputs of the first counter pulses, the output of the sign of the direction of rotation of the code setting block is connected through the first element to the control inputs of the first and second keys, the control inputs of the third and fourth keys enes to the input of the first NOT member, transferring the first output of the pulse counter via a second element is coupled to the first recording pulse counter input, a direct output of flip-flop soedi0

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with the input of the counting direction of the first pulse counter and the first inputs of the OR element and the first element AND, the output of the OR element is connected to the information inputs of the first and third keys, the output of the first element AND is connected to the information inputs of the second and fourth keys, the output of the pulse generator is associated with the counting the input of the first pulse counter, the outputs of the first, second, third and fourth switches are connected to the corresponding inputs of the bridge inverter, the outputs of which are the outputs of the device, characterized in that Then, in order to increase the reliability of operation due to the exclusion of through currents, a second pulse counter, a third element NOT and a delay code register, the bit outputs of which are connected to the corresponding information inputs of the second pulse counter, whose record input is connected to the output of the second element NOT, are entered into the device. and the counting trigger input, the transfer output of the second pulse counter is connected to the second input of the OR element, to the first input of the second element AND, and through the third element to the second input of the first second AND gate, the second input of the second AND gate connected to the output of the pulse generator, the delay information input code register are respectively connected to a second group of information outputs specifying code block, the second direction input pulse counter counting device connected to the common bus.

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Claims (1)

Claim A device for controlling an electric drive containing a first pulse counter, a trigger, two NOT elements, four keys, a code setting unit, a pulse generator, a bridge inverter, an OR element and two AND elements, the first group of information outputs of the code setting unit is connected respectively to the information inputs of the first counter pulses, the output of the rotation direction indicator of the code setting unit is connected through the first element to the control inputs of the first and second keys, the control inputs of the third and fourth keys are connected to the input of the first element NOT, the transfer output of the first pulse counter through the second element is NOT connected to the recording input of the first pulse counter, the direct output of the trigger is connected to the input direction of the counting of the first pulse counter and the first inputs of the OR element and the first AND element, the output of the OR element is connected to information the first inputs of the first and third keys, the output of the first element AND is connected to the information inputs of the second and fourth keys, the output of the pulse generator is connected to the counting input of the first 10 pulse counter, output The first, second, third and fourth keys are connected to the corresponding inputs of a bridge inverter, the outputs of which are the outputs of the device, characterized in that 15, in order to increase the reliability of operation by eliminating through currents, a second pulse counter is introduced into the device, the third element is NOT and a delay code register, the bit outputs of which are connected to the corresponding information inputs of the second pulse counter, the recording input of which is connected to the output of the second element NOT and the counting input a trigger, the second carry output of the pulse counter 25 is connected to the second input of the OR gate, the first input of the second AND gate and via a third NOT element with a second input of the first AND gate, a second input of the second AND gate 30 is connected to the output of the pulse generator. the information inputs of the delay code register are connected, respectively, to the second group of information outputs of the code setting unit, the input of the count direction of the second pulse counter is connected to the device common bus. 1 in 10 12 16 32 1 in 10 12 ^a tlllllllll 11111II11111111111111111II1111 11 | LL 5 tl__L_ί f L J L I I 1 1 1 1 “Er” 0'f I I J ------------------------------------------------- ----: ----- 1 -9". ? L ___ g Ti -—> - 3 f J ------------1- - ef ", <C— —E ” I *. r G ““ 3 f I ....................... -J 4 'g Fig 2 Compiled by S. Nikitov Editor N. Bobkova Tehred M. Morgenthal Corrector S. Shekmar, Order 1242 Circulation 415 Subscription VNI14PI of the State Committee for Inventions and Discoveries under the State Committee for Science and Technology of the USSR 113035, Moscow, Zh-35, Raushskaya nab., 4/5 Production and Publishing Plant Patent ”, Uzhgorod, 101 Gagarina St.