SU1626159A1 - Device for viewing simultaneously digital signals on oscillograph screen - Google Patents

Abstract

The invention relates to electrical measuring equipment and can be used to study equipment on digital integrated circuits. The purpose of the invention is to enhance the functionality and simplify the device. The trigger 17 in each of the channels allows you to select any of the inputs for synchronization, and the use of a common operating memory unit 6 makes more efficient use of its capacity. The device also contains the elements AND 7 and 11-13, the distributor 2, the digital-analogue converter 3, the triggers 4 and 5, the element OR 8, the counter 9 and the inverter 10. 1 Il.

Description

The invention relates to electrical engineering and can be used to study equipment on digital integrated circuits.

The purpose of the invention is the expansion of functionality by providing automatic synchronization from any of the η-single studied digital signals and simplifying the device.

The drawing shows a functional diagram of a device for the simultaneous observation of η-digital signals on the screen of the oscilloscope.

The circuit contains inputs 1. 1 ... 1. η devices, distributor 2, digital-to-analog converter (DAC) 3. triggers 4 and 5, block 6 of random access memory (RAM), element 7, element OR 8, counter 9, inverter 10. elements 11-13, input 14 of the initial installation devices, input 15 clock pulses, output 16 devices, trigger 17, inputs

18.1 ... 18. η channel setting.

Moreover, the first inputs of the elements And Ills are connected to the corresponding output of the distributor 2, the output of the element And 12 through the inverter 10 is connected to the second input of the element And 13, the output of which is connected to the corresponding odd input of the DAC 3, the output of the element OR 8 is connected to the input of the installation of trigger 4, the input the reset of which is connected to the input of the counter reset, with the input 14 of the initial installation of the device, with the input of the installation of the trigger 5, the output of which is connected to the control input of the RAM 6, the input address of which is connected to the output of the counter 9, the transfer output of which is single with trigger reset input 5, RAM selection input 6 is connected to the input of counter 9 and to the output of element And 7, the first input of which is connected to the input of the distributor 2, whose input is input 15 clock pulses, the second input of the element And 7 is connected to the output of trigger 4 , the output of the DAC 3 is the output 16 of the device. In each channel, the trigger setup input 17 is connected to the channel setup input 18, the trigger information information input 17 is connected to the logical unit bus, the trigger reset reset input 17 is connected to the input 14, the trigger input 17 is connected to the RAM information input by the output of the OR element 8, each input which is connected to the output of the element And 11 of the corresponding channel, the output of RAM 6 is connected to the second inputs of the elements And 12, the output of each of which through the inverter 10 is connected to the corresponding odd input of the DAC 3, each even input of the DAC 3 is connected to the output corresponding element And 12.

A device for the simultaneous observation of η-digital signals on the screen of the oscilloscope works as follows.

In the initial state, inputs 1.1 ... 1. η devices do not receive signals. Input 15 receives frequency F. The device is set to its initial state by the initial setting pulse (NU) at input 14. The NU pulse sets the direct output of trigger 5 to a high level, which sets RAM 6 to the information recording mode. The NU pulse will set the counter outputs to a low level and at the direct output of trigger 4 a low level that goes to the input of And 7, preventing the passage of frequency F to the counting input of counter 9.

Pulses of frequency F / n from the output of the distributor 2 are fed to the inputs of the elements And 11-13. At the output of RAM 6 there is no high level signal, therefore, the And 12 element is closed, and the And 13 element is open by the signal from the inverter. The pulses of the distributor 2 through the element And 13 of each channel arrive at the odd inputs of the DAC 3, causing a stepwise changing voltage at its output.

In this case, η-horizontal dashed lines will be displayed on the screen of the oscilloscope connected to the output 16 of the device. The number of dots in each of the lines displayed on the oscilloscope screen depends on the sweep installed on the oscilloscope. With a significant number of them, the user sees a solid line on the screen.

The first stage of the changing voltage at the output of the DAC 3 corresponds to each dashed line, for example, the lower dashed line a on the oscilloscope screen. The second stage of the changing voltage at the output of the DAC 3 corresponds to each dotted line of the dashed line b on the screen of the oscilloscope, etc.

Depending on the needs of the pulse, the channel settings can be applied to all inputs 18.1 ... 18. η or, optionally, to one of them.

Suppose the channel installation pulses are applied to all inputs 18 1 ... 18 p. At the same time, a high level is set at the direct output of the trigger 17 of each channel, which prepares AND 11 elements for reception via outputs 1.1 ... 1. η of the studied signals. Let the studied signals arrive only at inputs 1. 1 and 1.2. The pulses received at the inputs 1.1 and 1.2 of the device through the element And 11 of the corresponding channels will go to the inputs of the element OR 8.

From the output of the OR element 8, a high level is supplied to the counting input of the trigger 17 of all channels, confirming a high level at their direct outputs, and to the input of the installation of trigger 4, setting a high level at its direct output. It will allow the passage of the frequency F through the element And 7 to the input of the selection of RAM 6 and the counting input of the counter 9. At the outputs of the counter 9, codes will be generated that go to the address inputs of the RAM 6. Thus, information is written to the RAM 6 through the elements 14 11 and OR 8, arriving at the inputs 1. η device. At the moment of filling counter 9 (and, therefore, the end of writing in RAM of a single short-term process), a high level signal appears at its transfer output, which goes to the reset input of trigger 5 and sets a low level at its direct outputs, which sets the read mode in RAM 6 . The frequency F continues to flow through the And 7 element to the counting input of the counter 9, since it is possible to prohibit the passage of the F frequency through the And 7 element only by supplying a low level to its second input from the output of trigger 4 after supplying the NU signal to the reset output.

The outputs of the counter 9 are constantly (with the period of filling up the counter 9) the addresses of the RAM 6 cells being generated, the output of which high-level signals, passing through the elements 14 12 channels corresponding to the inputs 1.1 ... 1.Π, are fed to the even inputs of the DAC 3. causing step-changing voltage at its output. Thus, the user is given the opportunity to observe for a long time (before applying a signal to input 15) a single short-time process recorded in RAM 6 for inputs 1. 1 ... 1. p.

Stop and transfer the device to its original state by applying a pulse to the input 14 of the device.

If it became necessary to observe the process at inputs 1. 1, 1. 2, from the moment of time corresponding to the arrival of the signal, to input 1-3 of the device, then in this case the channel setting pulse is supplied after the pulse at input 15 only to input 18 3. Therefore , only in the third channel (corresponding to input 18.3) at the direct output of trigger 17 a high level will be established that allows the signal to pass through element 11 only from input 1.3 of the device. Incoming signal output

1.3 device, through the elements And 11 and OR 8 it enters the counting inputs of the triggers 17 of each channel and sets a high level on their direct outputs. From this moment, it is allowed to receive signals in RAM 6 from all channels of the device, i.e. automatic synchronization of signals received from the device’s channels from the signal is performed. received from the third channel.

Further operation of the device is similar to the described algorithm.

Claims (1)

Claim Device for simultaneous observation of η-digital signals on the oscilloscope screen, containing η-inputs of the device and, accordingly, l channels, a distributor, a digital-to-analog converter, first and second triggers, a RAM block, the first AND element, OR element, a counter, in each channel an inverter , the second, third and fourth elements And, the first inputs of which are connected to the corresponding output of the distributor, the output of the third element And through an inverter is connected to the second input of the fourth element And, the output of which is connected to the corresponding odd input of the digital-to-analog converter, the output of the OR element is connected to the installation input of the first trigger, the reset input of which is connected to the reset input of the counter, to the input of the initial installation of the device, to the installation input of the second trigger, the output of which is connected to the control input of the RAM block, whose address inputs connected to the outputs of the counter, the transfer output of which is connected to the reset input of the second trigger, the input The choice of RAM block is connected to the input of the counter and the output of the first ele cient And, the first input of which is connected to the input of the distributor, whose input is connected to the input clock, a second input of the first AND element is connected to the output of the first flip-flop, the output digital to analog converter connected to the output device, characterized in that. in order to expand the functionality and simplify the device, a third trigger is introduced into each channel, the installation input of which is connected to the channel installation input, the information input - with the Logic Unit bus, the reset input - with the initial installation input, the counting input - with the information input of the operational unit memory and with the output of an OR element, each input of which is connected to the output of the second AND element of the corresponding channel, the output of the RAM block is connected to the second inputs of the third AND elements, the output of each of which It is connected to the corresponding even output of the digital-to-analog converter.