SU1619256A1 - Division device - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-speed digital signal processing processors and arithmetic devices of high-speed digital and combined computing machines. In the device, the division of binary normalized numbers is accomplished by instrumental implementation of an iterative algorithm. The aim of the invention is to reduce hardware costs and increase speed for devices of an iterative type. To achieve the goal, a device containing three matrix multipliers 2-4, two adders 5.6 and register 1, two groups of elements HE / 8 and a pulse generator 13 are added, the connections between the blocks are organized in such a way that, while ensuring high speed prototype may reduce hardware costs by 15% compared with the prototype. 7. il. J

Description

The invention relates to computing and can be used in the construction of high-speed digital signal processing processors and high-speed digital arithmetic devices for combined computers.

The aim of the invention is to reduce hardware; cost and speed.

FIG. 1 shows a block diagram of the device; in fig. 2 is a graph of the function cf (a).

The device for dividing contains a register 1, matrix multipliers 2 - 4 adders 5.6, groups of 7.8 NOT elements, inputs 9.10 of the divisible and divisor devices and outputs 11 of the device, as well as input 12 of the device synchronization, generator of 13 pulses input 4 logical unit of the device input 15 logical zero device.

As the matrix multipliers 2, 3 can be applied chips

КР 1802BP3 or КР 1802ВР4. As the third matrix multiplier 4, the same microcircuit can also be used, but in this case it is necessary to feed signals to the sync input from an external or internal oscillator 13, the frequency of which is determined by the completion time of multiplication operations in multiplier 4 and summation in adder 6. For To achieve the highest speed for this device, it is advisable to use an asynchronous module as a multiplier.

As adders 5.6 can be used combiners of combinational type, for example, microcircuit series 155

The device implements an intraradiation process corresponding to the equation

x (K b (a) (a) -l, xk,

where a is a divider; b is the dividend;

CAA) 1.

The device works as follows.

The binary codes of the divisible b and the divider a in normalized form are fed to the inputs 9 and 10 of the device, respectively, and the divisor code is stored in register 1. The signals of the code

$

„

five

0

A switch from the outputs of register 1 is fed to the inputs of the first multiplier of multiplier 2, and the low-order (n-1) bits of it are also fed to the inputs of the elements of NOT group 7. The high bit of the divider code goes to the high bit of the first term of the adder 5. The inputs (p-1) of the least significant bits of the first term of the adder 5 receive signals from the outputs of the NOT elements of group 7. Given that the inputs of the second term of the adder 5 are connected to the bus of the logical zero of the device, and the transfer input of the adder 5 is connected to the bus logical one Itza, the output of the adder 5 ustanovits code approximate inverse of Cp value (a) 3-2a 1 / A (FIG. 2) which enters one of the inputs of the multipliers of the multipliers 2 and 3.

After a time sufficient to travel the signals from input 10 to the outputs of the adder 5, the starting clock pulse is fed to the input 12 of the device. As a result, the codes received at the inputs will be multiplied by multipliers 2.3, and their outputs will form the product codes a-C (a) and b- (L (a), respectively, which retain their value until the next signal arrives at 12.

From the outputs (n-1) of the least significant bits of the n of the most significant (without the signal of the higher bit, equal to one, since for the normalized numbers a (p (a) Ü1) of multiplier 2, the signals of the a-0f multiplier 4 are received) (a) -lj.

The signals of the b-cf (a) code from the output of multiplier 3 are fed to the inputs of the first term of adder 6, the inputs of the second term of which receive additional code signals from the multiplication result in multiplier 4. The additional code is formed by inverting the signals of multiplier 4 in the elements of group 8 and the arrival of the inversion signals at the inputs (p-1) of the lower bits of the second term of the adder, as well as the connection of the transfer input and the higher-order input of the second term of the adder 6 with the bus of the logical unit.

In the initial state of the device, a zero code 0.00, .. 0 is set at its outputs 11.

After the receipt of codes) at the inputs of the first term, the sum of an oracle 6

and taking into account the fact that the inputs of its second term still have a zero code, since a-ty (a) -fj. x 0.00 ... O, at the outputs of the adder 6, the first approximation code of the particular field b-y (a) -fa Cj) (a) -l is formed. xa) b-tp (a).

The signals of the x code from the outputs of the adder are fed to the inputs of the second factor multiplier 4, as a result of which the output of the multiplier 4 forms the product code a-tp (a) -ljx (1, which in additional form goes to the inputs of the second term for the next subtraction B - (| (a) sa s (a) -fi x ft. At the output of adder 6, the code of the next (second) approximation of the quotient is formed

X

{g

B. (A) (a) - Ochh

"one

The process of changing the codes in blocks 4 6.8 will be iteratively repeated until the device becomes stable at x xi when the reason for the continuation of the interaction process disappears. If x1 x (, from the interaction equation one gets (J (a) (a) x, from where it follows. Thus, after termination (termination) of the integration process in blocks 4,6,8, the outputs of the device 11 will determine the value of the quotient code calculated by in the accuracy of the younger category.

If the multiplier 4 is synchronized, then its synchronization input must be connected to the output of an external or internal pulse generator, the period of which must be slightly longer than the total time of the multiplier, summation, and delay in blocks 4.6, 8, respectively.

Claims (1)

Invention Formula A device for dividing, containing three matrix multipliers, two adders and a register, whose inputs are $ 0 five 0 five 0 five There are no inputs with the device divider, the register outputs are connected to the inputs of the first multiplier of the first matrix multiplier, the inputs of the second multiplier are connected to the outputs of the first adder and to the inputs of the first multiplier of the second matrix multiplier, outputs of which are connected to the inputs of the first addend of the second adder whose outputs are connected to the outputs device and with the inputs of the first multiplier of the third matrix multiplier, characterized in that, in order to reduce hardware costs and increase speed The device contains two groups of elements NOT and a pulse generator, the output of which is connected to the synchronous input of the third matrix multiplier, whose inputs are connected to the outputs of n-1 low-order bits of the first matrix multiplexer, whose synchronization input is connected to the synchronization inputs of the device and the second matrix multiplier, the inputs of the second factor are connected to the inputs of the divisible device, outputs n-1, where n is the size of the operands, the low bits of the register are connected to the inputs of the elements NOT the first the groups whose outputs are connected to the inputs n-1 of the lower bits of the first term of the first adder, the input of the senior bit of the first term of which is connected to the output of the higher digit of the register, the input of the logical unit of the device is connected to the inputs of the transfer and the senior bit of the second term of the second adder and the transfer input of the first adder, the input of the second term of which is connected to the input of the logical zero of the device, the outputs of the third matrix multiplier are connected to the inputs of the NOT elements of the second group, the outputs of which connected to the inputs of the n-1 junior bits of the second term of the second adder. Vto, l 10,000 0,0110,100 0,1010,110 (1111 /, shu a FIG. 2