SU1615773A1 - Movable object data transceiving device - Google Patents

Abstract

The invention relates to a technique for transmitting information from moving objects. The purpose of the invention is to increase the reliability of the transmitted information. The device contains on the transmitting part installed on the movable object, the setting devices of the transmitted information 1-1N, the shaper of the code sequence of signals 2, the modulator 3 and the transmitter 4, on the receiving part installed at the control point, the receiver 5, the demodulator 6, the clock generator 7, a block for changing the phase of clock pulses 8, a comparator 9, element 10, register 11, first and second shift registers 13 and 14. This device allows to increase the reliability of the received information by introducing frame synchronization, allowing recording information in the output register only at the moment of equality of the codes in the synchronization and information parts of the shift registers. 4 il.

Description

3S

3 $

40

FIG. 2

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Claims (2)

Claim 1. A device for transmitting and receiving information from a moving object, containing, on a transmitting part mounted on a moving object, transmitters of transmitted information, the outputs of which are connected to the inputs of a code sequence generator, the output of which through a modulator is connected to the input of the transmitter, the output of which is the radio channel input, at the receiving part, installed at the control point, is the receiver, the input of which is the radio channel output, the receiver output is connected to the demodulator input, register, outputs to which are the outputs of the device, characterized in that, in order to increase the reliability of the received information, a clock pulse generator, first and second shift registers, a clock phase change unit, a cycle synchronization pulse shaper, a comparator and the And element, the first and second are introduced at the receiving part the outputs of the clock generator are connected to the first and second clock inputs of the phase change block of the clock frequency, the output of which is connected to the clock inputs of the first and second shift registers, the demodulator stroke is connected to the information inputs of the clock phase change unit and the first shift register, the output of the latter is connected to the information input of the second shift register, the outputs of the first groups of outputs of the first and second shift register registers are connected to the inputs of the first and second groups of inputs of the pulse synchronizer, respectively whose output is connected to the first input of the AND element, the outputs of the second group of outputs of the first shift register are connected to the inputs of the first group of inputs of Arathor, the outputs of the second group of outputs of the second shift register connected to the data inputs of the register and to the inputs of the second group of inputs of the comparator, whose output is connected to the second input of AND ,, whose output is connected to the clock input of the register. 2. The device according to claim 1, characterized in that the clock phase change unit contains an NOT element, two OR elements, three AND elements, a trigger and two pulse shapers, the inputs of the HE element and the first pulse shaper are combined and are an information input of the block, output the element is NOT connected. It is connected to the input of the second pulse shaper, the outputs of the first and second pulse shapers are connected to the first and second inputs of the OR element, the output of which is connected to the first 1615773 10 the input of the first element AND, the output of which is connected to the counting input of trigger ¹ ger, the direct and inverse outputs of which are connected to the first inputs of the second and third elements AND, respectively, the outputs of which are connected to the first and second inputs of the second element OR, respectively, the output which is connected to the second input of the first And element and is the output of the block, the second inputs of the second and third And elements are the first and second ^ clock inputs of the block, respectively. FIG. 2 40. .4/ ......... ........ ' ^{And 11 11} - ¹ * .......— —I ιΑ— Figure 3