SU1598084A1 - Device for controlling three-phase d.c. voltage converter - Google Patents

Abstract

The invention relates to a converter technique. The purpose of the invention is to improve the quality of the converted voltage by reducing the harmonic coefficient. The device contains frequency master 1, a twelve-channel shift register 3, a pulse width modulator 22, three additional flip-flops 16, 17, 18, setup inputs connected to the outputs of the shift register 3, and three identical control signal generation nodes. Voltage regulation is provided by appropriate switching of cell keys by the method of partial pulse-width regulation. 3 il.

Description

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The invention relates to converter technology and can be used in the construction of centralized sources of secondary power supply with a sinusoidal stabilized output voltage.

The aim of the invention is to improve the quality of the converted voltage by reducing its harmonic coefficient.

FIG. 1 is a schematic diagram of a device for controlling a converter; in fig. 2 is a schematic of the power section of a three-phase DC / DC converter; in fig. 3 shows timing diagrams explaining the principle of operation of the device for controlling the converter, and the shape of the output phase voltage.

A device for controlling a three-phase converter of direct voltage includes a frequency adjuster 1 connected to frequency divider 2 by two, the output of which is connected to the counting input of the twelve channel shift register 3 with paraphase outputs Qi, Qi ... Qi2, Qi2. The indicated shift register 3 can be performed, for example, on twelve triggers 4-15 (only four triggers 4, 5 and 14, 15 are shown in Fig. 1) with cross-linking. The device also includes three additional JK-flip-flops 16-18, the counting inputs of which are combined and connected to the output of the setpoint 1 frequency. The installation J- and K-inputs of the triggers 16-18 are connected to the corresponding outputs of the twelve-channel register 3 shifts

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, a outputs Di, Di ... D3, Oz of these flip-flops 16-18 are connected to the inputs of three similarly executed nodes 19-21 of generating control signals Mji - Mj5. The remaining inputs of the nodes 19-21 are connected to the corresponding outputs of the flip-flops 4-15 of the 3-shift register and the S-output of the pulse width modulator 22. The latter can be made autonomous or synchronized from the setpoint 1 frequency.

Each node 19-21 contains two elements ZI-NO 23 and 24, two elements 2I 25 and 26, element ZI-2ILI-27, and two elements 2ILI-NE 28 and 29. At the outputs of elements 2I 25 and 26, control signals MAI and MAZ, defined by the logical expressions MAi QiQi2, MA3 QiQi2. The channel of node 19, designed to form the control signal MAS. contains elements ZI-NOT 23 and 24 and element ZI-2IL 27, connected in such a way that at the output of the latter a control is formed

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The main signal defined by the logical expression MA5 DiD2S Q2Qii + DiD2S Q2Qii. To generate control signals MA2 and MA4, two additional elements 2IL-HE 28 and 29 are used, the inputs of which are connected to the outputs of elements 2I 25 and 26 and ZI-2ILI 27 At the output of element 2IL-HE28, a signal MA2 MA1 + MA5 is generated, and at the output of element 2 OR-NOT 29 a signal MA4 MAZ + MA5.

The other two nodes 20 and 21 of the formation of the control signals are made similarly, taking into account the phase shift at an angle of 2/3 signals from the outputs of the distributor i pulses and triggers 16-18. In general, the logical expressions defining the links in each of them can be represented as:

Mjj QiQI + ii; Mj3 QiQi-Hi;

0 Mj5 DmDm + lSQKiQi + io + DmDm + iSQI + iQI + io; Mj-f-2 Mj + 1 + Mj5; Mj4 Mj3 + Mj5.

For phase A), the indices m and i are 1. For phase B,, for phase C,. It should be noted that if the resulting index of the signal Q turns out to be more than twelve (the number J of the K-flip-flops 4-15 of the pulse distributor) or the signal D is more than three (the number of additional J of the K-flip-flops is 16-18), then its value is equal to the resulting minus 12 or 13 with simultaneous inversion of this signal. Such an operation may be carried out repeatedly, until a condition is satisfied. The outputs Mji, Mj2, Mj3, Mj4, Mj5 of nodes 19-21 are connected via the amplifying-decoupling node 30 to the control inputs of the corresponding switches of the power section of the converter.

The constant voltage to three-phase converter (Fig. 2), which is controlled by the proposed device, contains three single-phase inverter cells 31-33, made in the form of two keys racks 34-45, with the keys 34-39 connected to the first (e.g., positive) converter power supply bus 46 is made in the form of fully controlled AC switches, and the adjacent keys of 40-45 racks are in the form of counter-parallel connected, for example, {5, transistor and diode. The middle points of the racks of the keys 34-45 of the inverter cells 31-33 are connected to the ends of the primary windings 47-49 of the respective transformers 50-52, and the middle points of the windings 47-49 are connected through the keys 53-55 (also made as keys 40-45, in the form of anti-parallel transistors and

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diode) to the first bus 46 power converter. The secondary windings 56-58 of the transformer 50-52 are connected in a star.

The principle of operation of the device for controlling the converter is illustrated by time diagrams (Fig. 3).

Frequency reference 1 synchronizes the operation of the device. Pulses of the form Ui from its output are fed to the input of divider 2 frequency, and also determine the frequency of operation of the modulator 22 pulse width. The pulses U2 are fed to the counting input of the register 3 shift pulses. The phase shift between the sequences of symmetric n - rectangular pulses, 01, a2, ... 012, ... 012 is. Each trigger 16-18 is synchronized by the corresponding signal from the output of the register 3 shift pulses, and a sequence of pulses Ui is fed to their counting inputs. As a result, the output signals Ui6-Ui8 are shifted by an angle n / 24 with respect to the signals Q, Qs and Qi2, respectively.

In order to control the value of the output voltage of the converter, the duration of the signal at the output of the pulse width modulator 22 is varied in accordance with the signal Da. This signal, as well as signals from the outputs of the register 3 shift pulses and triggers 16-18, are fed to the inputs of three nodes 19-21 generating control signals, keys 34-45 and 53-55 of the converter. After performing logical operations on the pulse sequences at the outputs of elements 25-29, new sequences of control pulses (signals) are defined, which are defined by the given logical expressions. The number of each element 23-29 in node 19 corresponds to the index of the received sequence of pulses, some of which are shown in FIG. 3. As a result, the switches 34-45 and 53-55 of the converter are switched in accordance with the developed algorithm. The adjustment pauses a and the additional pulses are introduced in this case at a certain conduction interval of the keys 34-39 and 53-55. With a symmetrical load of the converter connected to a star without a neutral wire, the phase voltage on the load (with the corresponding value of the adjusting pause a) has the form UA (Fig. 3).

Thus, the proposed converter allows to provide regulation of the output voltage in a certain range. When it changes

the relative value of the adjustment pause a from O to 1; the effective value of the output voltage varies from 0.866 Um to 0.645 Urn. The fundamental harmonic of the output voltage varies from 1.219 Dm to 0.901 Um. This method of regulation will allow stabilization of the output voltage of the converter when the supply voltage varies in the range of ± 15%, i.e. sufficient for most autonomous objects. The quality of the output voltage of the converter, determined by the harmonic coefficient of the output voltage Kg, varies from 0.094 to

 0.163 (with ai 0.5 Omax. Ul 1.06 Umaks Kg

0.197). In comparison with the known device, in the same range of variation of the output voltage, Kg varies from 0.094 to 0.405, and with Ui 1.06 Umaks, 283. Reducing the value of Kg will reduce the installed power of the output filter of the converter, improve its weight and dimensions, and increase its speed.

The proposed device for controlling the converter can be used in the construction of stabilized centralized sources of secondary power, when required.

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Coordination of nominal levels of load voltage and power supply and stabilization of the latter in case of power voltage fluctuations in the range of ± 15% with high quality of the output voltage. A small value of /, e, is provided by a filterless path, without complicating the structure of the power section of the converter.

Claims (1)

The formula was invented by a device for controlling a three-phase converter of constant voltage, including three single-phase inverter cells with a transformer output, each of which is made in the form of two key racks with control inputs Mji ... Mj4, where, B, C is an index phases, with the keys with control inputs Mj2 and Mj4, connected to the first power bus, made in the form of fully controllable AC keys, and the keys with control inputs Mji and Mj3, connected to the second power bus, in the form of opposite - parallel t a razistor and a diode, the midpoints of the key racks are connected to the ends of the transformer primary winding, the midpoint of which is connected via a key with a control input Mjs, also made in the form of an anti-parallel connected transistor and a diode, connected to the first power line of the converter containing a frequency adjuster, output connected through a frequency divider by two with a counting input of a twelve-channel shift register, paraphase outputs QI, Qi ... Qi2, whose Qia is connected to the corresponding inputs of three similarly formed units The control signals whose outputs, Mj2, ... Mj5 are intended to be connected to the corresponding control inputs of the said converter keys, are also connected to the output of the frequency adjuster, a pulse width modulator, an S-output connected to one of the inputs of the control forming units signals, to the remaining free inputs of which are connected the outputs Di, D1 ... D3, Oz of three flip-flops, the setting J- and K-inputs of which are connected to the outputs of the twelve-channel shift register so that,,, K2 Qs,, Phage. 2 0 five 0 . Their counting inputs are combined and connected to the output of the frequency adjuster, characterized in that, in order to improve the quality of the converted voltage by reducing the harmonic coefficient, the connection between the inputs and outputs of the control signal generation nodes is implemented to implement the following logical expressions: MjrQiQl-m: Mj3 QiQiH-ii: Mj5 DmDm-t-iSQi + iQi-t-io + DmDm-nSQn-iQI-no, Mj2 Mji + Mj5; Mj4 Mj3 + Mj5, where (9,17) and (3,5) respectively for (B, C). moreover, if the resulting index with Q is more than twelve or three with D, then its value decreases accordingly by 12 or 3 with simultaneous inversion of the given output signal and such a transition can be carried out repeatedly until the condition is satisfied. and. Ui and, U (S) Q, Oi ts, Q, i Uju,) U ()} J 141 (x4) Uzf, U2 (M ,,)) and Mg