SU1580534A1

SU1580534A1 - Ternary counting device

Info

Publication number: SU1580534A1
Application number: SU884618256A
Authority: SU
Inventors: Александр Сергеевич Галкин; Владимир Петрович Грибок; Виталий Емельянович Гордиенко; Анатолий Васильевич Воронецкий
Original assignee: Предприятие П/Я А-3759
Priority date: 1988-12-09
Filing date: 1988-12-09
Publication date: 1990-07-23

Abstract

Изобретение относитс к вычислительной и импульсной технике и может быть использовано в счетных схемах по модулю три. Цель изобретени - повышение надежности устройства в работе путем полного исключени "запрещенных" состо ний. Троичное счетное устройство содержит два RS-триггера 2 и 7, каждый из которых состоит из двух элементов И - НЕ 3, 4 и 8, 9, четыре двухвходовых элемента И - НЕ 10 - 13 и два многовходовых элемента И - НЕ 5 и 6. Подаваемые на входную шину 1 импульсы последовательно формируют на выходах элементов схемы сигналы, которые повтор ютс с периодом, в три раза большим, чем период входных импульсов, в том числе сигнал типа меандра (со скважностью два). 2 ил.The invention relates to computing and impulse technology and can be used in modulo three counting circuits. The purpose of the invention is to increase the reliability of the device in operation by completely eliminating the "forbidden" states. The ternary counting device contains two RS-flip-flops 2 and 7, each of which consists of two elements AND - NOT 3, 4 and 8, 9, four two-input elements AND - NOT 10 - 13 and two multi-input elements AND - NOT 5 and 6. Pulses fed to the input bus 1 sequentially generate signals at the outputs of the circuit elements that repeat with a period three times longer than the period of the input pulses, including a square-wave signal (with a duty cycle of two). 2 Il.

Description

Т 2 3 ts tsT 2 3 ts ts

Фаг. 2Phage. 2

Claims

Claim

AND NOT and two many AND NOT, the output of the primary element AND NOT the entrance of the first two

A ternary counting device containing two RS-flip-flops (on two AND-NOT elements each), four two-input elements of the input element of the th multi-input keys to the first input element AND-NOT and the R-input of the first RS-trigger, the S-input of which is connected to the first the input of the first multi-input AND-NOT element, and the Q-output is connected to the second input of the first two-input AND-NOT element, the output of which is connected to the second input of the first multi-input AND gate, the third input of which is connected to the Input bus, the first input of the second multi-input element AND NOT and the first input of the second two-input element AND-NOT, the second input of which is connected to the output of the third two-input element AND, the first input of which is connected to the output of the second two-input element AND and the S-input of the second RS-trigger, Q-output which is connected to the first input of the fourth two-input AND-NOT element, and the R-input is connected to the output of the second multi-input AND-NOT element and the second input of the fourth two-input AND-NOT element, characterized in that, in order to increase reliability, work by eliminating prohibited states , the output of the fourth two-input AND-NOT element is connected to the second input of the second multi-input AND-NOT element, the 'third input of which is connected to the S' input of the second RS-trigger, the Q-output of which is connected to the first input of the first multi-input AND element, the second input which is connected to the second input of the third two-input AND-NOT element, and the fourth input is connected to the output of the second multi-input AND-NOT element.

FIG. 2