SU1580524A1 - Pulsing frequency-phase detector - Google Patents

Abstract

The invention relates to radio engineering and pulse technology. The purpose of the invention is to maintain a steady state operation when the reference signal disappears. Pulse frequency-phase detector contains the first, second, third, fourth and fifth D-triggers 1-5, the first, second and third element And 6-8, about element OR 9, integrating element 10, the first and second pulse shapers 11 and 12, RS flip-flop 13 and first and second multiplexers 14 and 15. Introduced third, fourth and fifth D-triggers 3-5, RS-flip-flop 13, first, second and third elements AND 6-8 and element OR 9 allow determine the presence of frequency detuning. Moreover, the direct output of the fourth D-flip-flop 4 determines the sign of the frequency error. The fifth D-flip-flop 5, depending on the magnitude of the detuning, determines the frequency or phase mode of the detector. In the frequency mode, the inputs from the integrating link 10 receive a signal from the output of the fourth D-flip-flop 4, and in phase mode - signals from the inverse outputs of the first and second D-flip-flops 1 and 2. When the reference signal at the input of the second pulse conditioner 12 n The D-flip-flop 5 does not change its state. 3 il.

Description

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The invention relates to radio engineering and can be used in pulsed and digital phase synchronization devices, frequency synthesizers, where a wide bandwidth is required when the reference signal disappears.

The aim of the invention is to maintain a steady state operation when the reference signal disappears.

FIG. Figure 1 shows the structure and electrical circuit of a pulsed frequency-phase detector; in fig. 2 and 3 are the stress plots at various points of the device at different misalignments in frequency.

The pulse frequency-phase detector contains the first 1, second 2, third 3, fourth 4 and fifth 5 D- (riggers, first 6, second 7 and third b elements AND, element OR 9, integrating element 10, first 11 and second 12 pulse converters (PI), RS-trigger 13, the first 14 and the second 15 multiplexers, which can be performed on a two-channel multiplexer.

The detector works as follows.

D-flip-flops 3 and 5 and the first element AND 6 provide fault detection, the signal of which is recorded in D-flip-flop 5. RS-flip-flop D-flip-flop 4 serves to determine the frequency deviation T / ta, information about which is stored in D- trigger 4.

Elements 7, 8 and 9 serve to reset the signal Fault (setting D-flip-flop 5 to one). Multiplexers 14 and 15 are used to switch the control signals of the integrating link 10 in such a way that in the absence of a signal Failure (D-flip-flop 5 in one state) to the output of the second multiplexer 15, phase-mismatch signals taken from the outputs of the D-triggers 1 and 2 pass. When the D-flip-flop 5 is in the zero state, the signals taken from the D-flip-flop 4 (giving information about the sign of the frequency deviation) are passed to the multiplexer output.

The signal acts on the first FI 11, which at the direct output generates pulses of the level of a logical unit, the duty cycle of which is more than two. The reference signal acts on the second PI 12, which generates pulses

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similar duration. The operation of the pulse frequency-phase detector occurs in such a way that the fronts of the pulses at the inverse outputs of the first 11 and second 12 PIs (trailing edges at their forward m1 and ix outputs) coincide.

In the initial state on the direct output of the second FI 12 (Fig. 2a, interval / 3t), the logical zero level can exist for a long time, while the D flip-flop 2 is maintained in the same state (on its inverse output the level of the logical unit, Fig. 2c). At this time, the first FI 11 sets the zero state of the D-flip-flop 1 (Fig. 2d) and the single state of the D-flip-flop H (Fig. 2e). This state of the triggers 12, 5 and 4 is undefined and depends on the processes that took place in the past interval of the reference signal. Suppose that earlier (or after switching on the device) the fact that the signal frequency did not match the required reference frequency was not established. This means that the D-flip-flop 5 is in the single state (Fig. 2h), so that the inputs of the integrating link 10 are connected to the outputs of the flip-flops 1 and 2. The D-flip-flop 4 state in this case is insignificant and for definiteness we take it as a single ( Fig. 2i).

With the appearance of the reference signal causing the appearance of pulses at the output of the second PHI 12 (Fig. 2a), the order of further operation of the device depends on how the pulses of the second FI 12 correlate in time with the pulses coming from the output of the first FI 11 (Fig. 26). While these pulses partially overlap in time, one of the D-flip-flops 1 or 2 is set to one for the time from the trailing edge of the first time from the overlapping pulses to the trailing edge of the second. So, in the first pair of overlapping in time pulses of the first 11 (Fig. 2b) and the second 12 (Fig. 2a) of the FI, the D-flip-flop 1 (Fig. 2d) is set to one at the time of the positive edge of the pulse at the inverse output of the second FI 11, because at this time on the information input of D-flip-flop 1 a high signal

level from the output of the first FI 11. The last signal, acquiring a low level value, resets the D-flip-flop 1 to the zero state. In the second and third pairs of overlapping in time pulses of the first 11 and second 12 FIs, a similar effect takes place already on D-flip-flop 2 with its setting to one state and returning to zero, which is caused by the change of phase ratios of the input signals. FIG. 2 shows the case when the frequency of the signal pulses is higher than the frequency of the reference signal. In addition, the signals from the inverted outputs of the flip-flops 1 and 2 affect the setup inputs of the RS-flip-flop 13, which in this case captures information about the temporal ratios of the pulses of the first 11 and the second 12 phi, set to one when the pulses of the second phi are ahead 12 of the corresponding pulses first phi 11 and zero otherwise. The pulses from the inverse outputs of the D-flip-flops 1 and 2 also act on the second 7 and third 8 elements AND, which, in addition, are controlled by the output signals of the D-flip-flop 4. At the same time, while the D-flip-flop 5 is in the single state, the state D-trigger 4 is indifferent. Thus, in the supposed state of the logical unit of D-flip-flop 4, the second element AND 7 and the element OR 9 can pass pulses to the installation input of the D-flip-flop 5, without changing, but only confirming the single state of the latter.

The pulses of the reference frequency from the second FI 12 also act on the clock input of the D-flip-flop 3, and their leading edge sets it to the zero state if at this time a high level acts on the installation input of this trigger (and on the information one - low) from the first FI 11. The return of the D-flip-flop 3 to the state of the logical unit is performed by the appearance of the next pulse of the first PI 11. For this case, such transitions of the D-flip-flop 3 (Fig. 2d) occur under the influence of the first, fourth and next successive pulses. supporting frequencies.

In the considered part of the device, the aim is to detect synchronization, the criterion of which

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is the absence of overlap of the pulses of the first 11 and second t2 PI, more precisely, the appearance of the reference frequency pulse in the pause between the pulses of the signal. So, a similar situation takes place during the action of the fourth pulse of the reference signal, the trailing edge of which, through element 6 (Fig. 2k), acts on the clock input of the D-flip-flop 5, writes into it that state (Fig. 2h), in which D-flip-flop 3 is located, because the output of the latter is connected to the information input of D-flip-flop 5. Thus, if there is no signal pulse for the duration of the pulse of the reference signal, D-flip-flop 5 is set to the zero state, which is a sign of failure. Further impact of the pulses on the clock input of the D-flip-flop 5 is prohibited by issuing from its output the potential of a logical zero to the first And 6 element.

At the moment of the D-flip-flop 5 going to the zero state, the positive edge of the signal from its inverse output, affecting the clock input of the D-flip-flop 4, records that state (Fig. 2i) that the RS flip-flop 13 ( Fig. 2e). Since the state of the RS flip-flop 12 depends on the mismatch of the falling edges of the signal pulses and the reference signal when these pulses are still partially overlapped, the D-flip-flop 4 records essentially the information about the directions of mutual displacement of the said pulse sequences i.e. about the sign of the mismatch in frequency. D-flip-flop 4 at the moment of fixing a fault with a positive edge of the signal from the inverse output of D-flip-flop 5 is transferred to the zero state.

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The criterion for returning to the initial state (setting to unit D of flip-flop 5) is the occurrence of such an overlap of signal and reference pulses, in which the error of their trailing edges has the same sign as before the frequency control was turned on. To this end, the outputs of D-flip-flop 4 open only one of the elements AND 7 or 8, preparing it to pass to the installation input D-flip-flop 5 of the corresponding signal, which in

The case being considered must be formed by a D-trigger 2.

FIG. Figure 3 shows the processes in a pulse frequency-phase detector when pulses of a reference signal appear, which generate pulses at the output of the second FI 11 (Fig. 3a), when the first of them does not overlap with a signal pulse (Fig, 3b). Here, the synchronization failure is detected | as in the previous case, since the D-flip-flop 3 detected the appearance of a pulse of the reference signal (Fig. A) and by the time of its falling edge would not have been cleared by a signal pulse. Therefore, the D-flip-flop 5, at the time t, is set to the zero state (Fig. 3h), including the frequency adjustment of the detector. However, due to the fact that previously the overlap of the compared pulses was not observed, the state of the RS flip-flop 13 is not defined (let us accept it, as before, as a single one, Fig. Ze). Therefore, at the time of detection of a fault, a signal of the opposite sense can be written to D-flip-flop 4 — in this case, an increase in the frequency, although it actually needs to be reduced.

However, after several periods of oscillation of the reference signal based on the analysis of the direction of change of the overlap of the compared pulse, the included frequency control is turned off (time t) and then turned back on (time t3) with the adjusted frequency detuning value.

Thus, in the proposed device, frequency and phase control is performed on a reference signal, which can affect irregularly and disappear.

Claims (1)

Invention Formula Pulse frequency-phase detector containing the first, second, third and fourth D-triggers, the first, second and third elements AND, as well as the OR element and the integrating element, the output of which is the output of the pulse frequency-phase detector . ,, - 25 30 at 20 35 40 45 50 The inverse output of the fourth D-flip-flop is connected by the first input of the third element I, characterized in that, in order to maintain a steady state of operation when the reference signal disappears, the first pulse shaper, whose input is the signal input, direct and inverse, is input into it. the outputs of the first pulse driver are connected respectively to the D and R inputs of the first D-flip-flop, the D input of the third D-flip-flop, the C-input of the second D-flip-flop and the S-input of the third D-flip-flop, the second pulse shaper, whose inputIt is the input of the reference signal, the direct and inverse outputs of which are connected respectively to the D and R inputs of the second D-flip-flop, to the C-inputs of the third and first D-flip-flops and to the first input of the first element And, RS-flip-flop, S- and R-inputs of which are connected respectively with inverse outputs of the first and second D-flip-flops and with the first input of the second element And the second input of the third element And, the outputs of the second and third elements And are connected to the inputs of the element OR, the output of the RS-trigger is connected with the D input of the fourth D-flip-flop, the fifth D-flip-flop, S-, D- and C- the moves of which are connected respectively to the output of the OR element, the output of the third D-flip-flop and the output of the first element AND, the second input of which is connected to the output of the fifth D-flip-flop, as well as the first and second multiplexers, the outputs of which are connected respectively to the first and second inputs of the integrating link , the first inputs of the first and second multiplexers are connected respectively to the output of the first D-flip-flop and the inverse output of the second D-flip-flop; the control inputs of the first and second multiplexers are connected to the inverse of the fifth D-flip-flop, which is also connected to the C-input of the fourth D-flip-flop, while the output of the fourth D-flip-flop is connected to the second input of the second element And and to the second inputs of the first and second multiplexers.