SU1562966A1 - Device for selection of asynchronous signals on basis of criterion "m out of n" - Google Patents

Abstract

The invention relates to automation and computing and can be used in computing devices with increased reliability. The aim of the invention is to simplify the device. The goal is achieved by writing asynchronous signals to the corresponding bits of register 1 and sequentially reading them. The verification of criteria M of N is carried out using the comparison scheme 10. 1 Il.

Description

The invention relates to automation and computer technology and is intended to work in redundant devices.

The device majorizes ³ asynchronous signals according to the criterion M from N.

The purpose of the invention is the simplification of the device. Ιθ

The drawing shows a block diagram of a device

The device for the majority choice of asynchronous signals contains the first N bit register 1 (by the number of ed устройства device inputs'), a group of input signals And 2, elements And 3 And 4, element OR 5, element 6 delay, element 7 delay, one-shot 8 , meter 9, comparison circuit 10 and second-2Q swarm register 11. The drawing also shows information inputs 12, clock input 13 and output 14 of the device.

The device operates as follows. 25

In the initial state, all the triggers of the shift register 1 are set to state 0, the one-shot 8 is in its stable zero state, Counter 9 is also set to zero. The code of number M is entered in register 11. The stable state of the one-shot 8 forms a single signal at the inputs of the elements And 2 and a zero 'signal at the input of the element And 4 "The signals arriving at the information inputs 12 ^ 5 set the corresponding triggers of register 1 to state I", at the same time the signals are fed to the inputs of the OR element 5. The first input pulse received by the information input 12, delayed by the delay element 7 · by the time during which asynchronous signals are collected, is fed to the input of a single-shot 8. One-shot Atator 8 generates a pulse by closing the input elements And 2 and allowing the passage of clock pulses through the And 4 element to the input of the shift register 1, shifting the information recorded in the register 1, delayed by the transients in the shift register by the element. 6 clock pulse arrives at the input of the installation in the state ”0 of the trigger of the first category of the shift register 1 and at the input of the element And 3, As a result of the passage of N clock pulses to the input of the counter 9 will receive as many pulses as the number of triggers was set to state 1, If the number of summed units in the counter 9 is not less than the code recorded in the register 11, then at the output of the comparison circuit 10 a single signal is generated to the output of the device.

Claims (1)

Claim A device for selecting asynchronous signals according to the criterion M from Ν, containing a group of input elements AND, first and second registers, first and second elements AND, an OR element, a first delay element, and the outputs of the input elements AND groups are connected to the information inputs of the first register, and the output The OR element is connected to the input of the first delay element, characterized in that, in order to simplify the device, a second delay element, a one-shot oscillator, a counter and a comparison circuit are introduced into it, and the first inputs of the input elements AND groups are connected s with information inputs of the device, and the second inputs of the elements AND groups are connected to the inverse output of the one-shot, the input of which is connected to the output of the first delay element, 'direct output, the one-shot is connected to the first input of the second element And, the second input of which is connected to the clock input of the device, output the second element And is connected to the shift input of the first register and through the second delay element to the installation input at 0 low order of the first register and the first input of the first element And, to the Second input of which is connected. information Rational. the high-order output of the first register, the output of the first AND element is connected to the summing input of the counter, the information outputs of which are connected to the first group of inputs of the comparison circuit, the outputs of the second register are connected to the second group of inputs, and the output of the comparison circuit is connected to the output of the device, the outputs of the input elements And the groups are connected to the inputs of the OR element.