SU1545224A1 - Device for interfacing computer and subscriber - Google Patents

Abstract

The invention relates to automation and computing and can be used for pairing. The purpose of the invention is to reduce the amount of equipment. The device contains a decoder 1, a group of elements And 2, a register 3, a group of memory blocks 4, a group of switches 5, a timer 6, a trigger 7, a pulse generator 8, an element 9, a frequency divider 10, a counter 11, a memory node 12, an element delays 13, register 14, address bus 15, bus 16 data, device outputs 17, counter 18. 1 Il.

Description

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The invention relates to automation and computing and can be used for pairing.

The invention is a reduction in equipment.

The picture shows the proposed mustache.

The device contains a decoder I, a group of elements I) 2, a register 3, a group of blocks 4. 1 ... A, memory p (n is the number of subscribers), a group of switches 5.1, .. 5, p, timer 6 formed by trigger 7 pulse generator 8, element 1 9, frequency divider 10, counter 11, the memory block contains wye 12 memories, delay 13 d 13, register 4, system address bus 15, sewed 16 data, 1 7 .1. . . 1 7 .p device, counter 18.

The device works as follows (i at a time.

Vshpny processor places HI this dark bus 16 address (A), corresponding to output 17.1, which is decrypted by decoder 1 and unclamps one of the elements AND 2. Then the processor generates a write control signal on the system bus 16, which is the spike of the open elements And 2 Pro-HI checker 11 or trigger 7 or i 1 Igr 3, or block 4, and kits, di-pye (D), placed on the system | yin 16, to the corresponding address.

Vn 14, an external processor enters into a node) 2, which can be four-bit, a house of blocks 4 and a form. Node 12 can be built on the chip 1802IDP1, where logical input (only information is written) is supplied to the read input of node 12 connected to the system bus, and logical unit is fed to the input of information recording mode of another port (only information is read). Consequently, at the same time it is possible to form K after-J3 i g concessions, like all K 12 points. 3 TRM external processor writes in peri 3 words, some word, to 1kg switch 5 signal from which BiLvoai depigel 10 frequency skip Hi i -p-od correlating ts hv 1 nd switch i 5. Fir Tir-rc KH determines whether MiCToiv is considered information 11 11 1, that is, IT g TV y not r io slots i n w hI ii, PD 1 g i de ps 10 g gogy shch g r i (,,

10, the operation of units 4 on the P-particles is possible, which increases the efficiency of diagnosis. For switches with P outputs divider 10, IKln register bits 3 are required. For four switches and eight outputs divider 10, 4 In 8 or 12 bits of register 3 is required. Usually registers

16 bits, so one register can provide a fairly wide range of operation of the device.

Then, a non-zero initial state, which determines the length of the test sequence, is written into the counter П. At the same time, at the output of counter 11, a logical unit is formed, allowing the opening of element II 9 (at the output of counter O

Q with zero counter content). AT

nt, in the same way, the processor 7 writes a logical unit to the trigger 7, and from the output of the generator-8, the pulses start to arrive

5 4PiP3 element I 9 to the 10 o'clock divider. At the same time, on nodes 4 from the outputs of the frequency 10 through frequencies via commutator — G11 i, the unit synchronizes the frequencies and is determined programmatically.

Q 3 gi sync signal i, arriving at the counting input of the counter 18, causes the sequential reading of information from the node 12. The counter 18 is automatically reset each time the information is written to the node 12

processor with the same recording release signal passing through the corresponding AND 2 element to the corresponding input of node 12. Thus, before testing starts, counter 18 is always zero. Counter 18 Generates addresses that determine how information is read.

Obviously, the order of reading

5 information must coincide with the order of recording information, otherwise the sequence may be distorted 17.1-17. Know the law of change of addresses. Formed by the counter 18, it is not difficult

programmatically organize and record information at node 12 at addresses subject to this law. The same sync signal, which is fed to the input of the Re / Kim readout information of the node 1 2 and the synchronization input of the register 14.) Delay 13 delay delayed reading of the site 12 at the corresponding address, onpt „nf Lennp- (TORCH

com 18, and simultaneous recording of this content into register 14. With a continuous stream of clock signals, the contents of node 12 are sequentially overwritten into register 14, from where they go to outputs 17. At outputs of register 14, which is easy to implement on a 589IK12 chip, a sequence is calculated by the processor. In the absence of sync signals, nothing is recorded in register 14. To transfer the outputs of register 14 to the high-resistance state, is the input of Mode selection 0), the signal to which can come from one of the outputs of the port of node 12 connected to register 14. Writing a prohibition signal to the corresponding bit, you can thus prevent the issuance of 17 prohibited combinations of signals.

To stop the generation of the sequence 17, the counter 11 is used, which is set by software. During the formation of clock pulses at the output of element II 9, pulses are received at the subtracting input of counter 11, reducing the contents of counter 11. When reaching the zero state of the counter at its outlet, a logical zero is formed, which is fed to one of the inputs of the element And 9 and prohibits the further passage of pulses. Thus, writing data to counter 11 during the preparation of node 12 for generation is a sequence: it determines the length of the sequence. The processor, after a time slightly longer than the generation time of the sequence, zeroes trigger 7, writing a logical zero into it, which locks AND 9 and makes it possible to prepare node 12 for another procedure.

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Before the next generation, the register 3 is taken into account, and the counter II records nn-J data. The last logical unit is the trigger 7, and since the states of the trigger 7 and the counter I1 are non-zero, the pulses from the generator 8 again begin to flow through the frequency divider 0 and cokmut tl 5 into nodes 4, etc. All testing procedures are carried out similarly.

Claims (1)

The invention of the device for interfacing a computer with 15 subscriber, containing; decoder; A group of elements, a register, characterized in that, with the reduction of equipment, a group of memory blocks, a group of switches and a timer are entered into it, the information inputs of the decoder and the address inputs of the memory blocks of the group are inputs to the device the computer bus, the coldplay inputs of the register, the timer, and the information inputs of the memory blocks of the group are the inputs of the device for connecting to the informational computer GUI, the outputs of which are connected to the inputs of the subscribers, the decoder moves are connected to the formalisable poises of the elements AND groups, the control inputs of which are the device input for connecting to the computer synchronization output, the outputs of the elements AND groups are connected to the enable and start inputs of the timer, register synchronization inputs and group memory blocks resolution inputs, the timer outputs are connected with the information inputs of the group switches, the control inputs of which are connected to the register outputs, the outputs of the group switches are connected to the synchronous inputs of the group memory blocks. 25 35 40