SU1539843A1 - Single-digit direct-access storage with error correction - Google Patents

Abstract

The invention relates to computing and microelectronics and can be used to create storage devices with integrated error correction in the integrated design. The aim of the invention is to increase the reliability of the device. The device contains the main and additional drives, the elements EXCLUSIVE OR, from the first to the seventh, and the elements AND, from the first to the third. The purpose of the invention is achieved by the fact that in each cycle of accessing the device, in addition to selectable information and check bits of the row and column of the iteration code, all remaining check bits are read and checked by parity, which allows detecting errors in check bits, correcting them and restore the true value in the additional drive in the cycle of recording the circulation cycle. 2 Il.

Description

The invention relates to computing and microelectronics and can be used to create storage devices with integrated error correction in the integrated design.

The aim of the invention is to increase the reliability of the device.

FIG. 1 shows a diagram of a one-bit random access memory with built-in error correction; in fig. 2 is an example of an array of information and check bits for which the dashed and solid lines indicate the bits read from the additional and main drives, respectively.

The device contains the main storage 1, the first 2 and the second 3 elements EXCLUSIVE OR, the first element AND 4, the third 5 and the fourth 6 elements EXCLUSIVE OR, information output 7 and device input 8, control input 9 of the device, additional storage 10, fifth element EXCLUSIVE OR 11, second 12 and third 13 elements AND, sixth 14 and seventh 15 elements EXCLUSIVE OR;

The device works as follows.

The correction of one-time errors in the array of information bits D1-D16 (Fig. 2) in the proposed single-bit random access memory (RAM) is based on the use of an iterator. coding code. Therefore, the device includes an additional 1U check bits accumulator (C1 – C8)

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with so

00 4

with

and a single coding / decoding unit built on logic elements 2-6 and 11-15. In order to simplify the description of the device, the address chains of the sampling of the memory elements (ES) of the main 1 and additional 10 drives are excluded from its composition.

Since the proposed device with error correction has one-way organization, any access to it begins with reading data from the main 1 and an additional 10 drives. If external access to RAM is made in the write mode, the read data is modified and overwritten in drives 1 and 10. In the external read mode, the read value restores the true value of the selectable bit (fed to the first output of the main drive 1), which is transmitted to the information output 7 devices.

In the device, taken as a prototype for one cycle of accessing the DL bit, the information bits D2, D5, Db, D7, D8, DY, DY and check bits C2 and Sb are read, and the contents of the check bits C2 and Cb reflect respectively, the results of modulo 2 summing the content bits of the row and column, at the intersection of which the desired dB is located. It should be noted that the separation indicated in FIG. 2 arrays of bits for rows and columns is conditional, since in a real matrix all EA are discharged in one row and are selected in one cycle of accessing RAM.

In a known device, a parity check is performed for the row (EXCLUSIVE OR 2 element) and the column (EXCLUSIVE OR 3 element) for the selected bits, and when parity is violated for both the row and the column, the AND 4 element simultaneously generates a level signal indicating the element EXCLUSIVE OR 5 on the need to invert the contents of the bit db. In the external recording mode, the corrected content of the dB bit is compared with the data bit, received at the information input 8 of the device, and in case of a mismatch, a signal is generated for the simultaneous inversion of the contents of the check bits C2 and Sat. Thus, the considered error correction tools

0

5 5

d5

0

errors can only be eliminated in the main storage unit 1 ES. If an error occurs in any checkpoint, then a simultaneous parity violation for the row and column is not observed and, consequently, such an error persists either until the RAM is turned off and the next time switching on the power supply of the initial installation of its EA, or until the occurrence of an error in any driver of the D1-D16 and C1-C8 arrays, which leads to failure of the device.

In contrast to the known device, in the proposed RAM, in each write and read cycle, in addition to the information and check bits listed above, all the remaining check bits (C1, SZ-C5, C7, C8) are also counted. This allows for any access to RAM to check parity for all check bits using EXCLUSIVE or 11. If, for example, an error occurs in bit C2, it is detected by AND 12, corrected by EXCLUSIVE OR Z and overwrites additional storage 10. In is--. The board of error in the discharge category is an element AND 13 and an element EXCLUSIVE OR 15.

Thus, the advantage of the proposed device is to increase the reliability of the RAM by detecting errors in the control bits of the complete data words, correcting them, and overwriting the corrected data into an additional drive.

Claims (1)

Invention Formula A one-bit operative memory device with error correction, containing the main drive, outputs to be selected when addressing the bits of the row and columns in which the first and second elements of the first and second elements are connected to the inputs of the first and second elements, respectively, whose outputs are connected to the inputs of the first element And, the output of which is connected to the first input of the third element EXCLUSIVE OR, the second input of which is connected to the output of the information bit of the main accumulator, and the output is for5 1 a device's output and connected to the first input of the fourth element EXCLUSIVE OR, the second input of which is the information input of the device and is connected to the information input of the main drive, The control input of which is the control input of the device, characterized in that, in order to increase reliability, an additional accumulator, the fifth, sixth and seventh elements EXCLUSIVE OR, the second and third elements AND, the output of the control bit of the additional accumulator corresponding to the selected row of the main drive, is connected to the first additional input of the first element EXCLUSIVE OR, to the first output of the fifth element EXCLUSIVE OR, and to the first input of the sixth element EXCLUSIVE OR, you the course of which is connected to the first information input of the additional accumulator, the output of the control bit of which corresponding to the selected column of the main accumulator is connected to the first additional input of the second element SPARK ZEVZ6 PARTICIPANT OR, with the second input of the fifth element EXCLUSIVE OR, and with the first input of the seventh element EXCLUSIVE 5 OR, the output of which is connected to the second information input of the additional storage device, the outputs of the control bits corresponding to the unselected rows and columns of the main storage unit, connections to the inputs of the group p that EXCLUSIVE OR element whose output is connected to the second inputs of the second and third elements AND, the first inputs of which are connected to the outputs of the first and second elements EXCLUSIVE OR, respectively the outputs of the second and third elements AND are connected to the third inputs of the sixth and seventh respectively EXCLUSIVE-20 OR, the second inputs of which are connected to the output of the fourth element EXCLUSIVE OR, the information output of the main storage device is connected to the second additional inputs 25 of the first and second elements EXCLUSIVE OR , the control input of the additional storage device is connected to the control input of the device. 9 o- 7th FIG. g